Webinar: GaN for DC to DC Converters and Voltage Regulators

Tuesday, August 28, 2018 8:00 AM (UTC-08:00) Pacific Time (US & Canada)
Webinar: GaN for DC to DC Converters and Voltage Regulators
Location: Online

GaN for DC to DC Converters and Voltage Regulators Speaker: Steve Sandler, Picotest

Alex Lidow stated that for the first time in 60 years, we have a semiconductor that outperforms silicon in every metric. This is a bold statement, especially considering that Alex Lidow also co-invented the silicon HEXFET that is the technology that is being displaced by GaN.

GaN offers many advantages compared to silicon MOSFETS, including smaller size, lower on state resistance, more stable gate voltage, much lower capacitance resulting in higher speed, lower inductance connection inductance and manufacturable using existing silicon wafer fabs and the promise of lower cost.

With all of these benefits, mass adoption should be instantaneous, right? Yet, engineers are slow to change, in part due to a lack of credible information and in part due to fear of the unknown. In this webinar we’ll answer these important questions, provide the essential information you need and allay your fears:

  • Why all the fuss about GaN?
  • Should I really be interested and HOW interested?
  • Can we just replace the Si devices with GaN devices?
  • What are the pros, cons and some of the pitfalls?
  • What topologies are best suited to GaN?

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Tuesday, September 25, 2018
Location: Portland, OR

GaN based Switched Capacitor Three Level Buck Converter with Cascaded Synchronous Bootstrap Gate-Drive Scheme Speaker: Suvankar Biswas, Ph.D., Senior Applications Engineer

With the power architecture transition from a 12 V to 48 V rack in modern data centers there is an increased interest in improving 48 V power conversion efficiency and power density. A three-level GaN based converter provides a high density and high efficiency solution. In this paper, we will introduce a high performance GaN based switched capacitor three level buck converter for 48 V applications. To fully utilize GaN technology in multilevel topologies, an improved cascaded synchronous bootstrapping technique is also proposed. The proposed gate driving technique is smaller and simpler than the previous gate driving techniques employed in GaN based multilevel topologies and offers tight gate voltage regulation. For experimental verification, a three-level switched capacitor buck converter with the improved gate drive scheme and closed loop flying capacitor balancing is compared against a traditional buck converter. In order to demonstrate a possible further application of the gatedrive scheme, a higher voltage (400 V) prototype is built, with improved experimental results over a regular half-bridge prototype. A simple startup protection scheme using Zener diodes is also verified, which removes the need for full voltage rated switches altogether. Finally, an improved 48 V to 12 V three-level prototype is discussed which combines the benefit of using lower rated GaN devices along with inductor size reduction.

IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA 2018)

Wednesday, October 31, 2018 - Friday, November 02, 2018
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA 2018)
Location: Atlanta, GA

Evaluation of GaN based Multilevel Converters Speaker: Suvankar Biswas, Ph.D., Senior Applications Engineer

With the significant reduction in board space occupied by the smaller GaN transistors, topologies that require a greater number of active devices as a tradeoff for reduced passive size, the main barrier to higher density, have become attractive. Switched capacitor multilevel converters1 are good examples of topologies that can effectively reduce or eliminate passive components. Two GaN based prototypes (three-level converters), one for a low voltage (LV) 48 V server application and the other for a high voltage (HV) 400 V power factor correction (PFC) circuit are discussed in this paper. Significant efficiency gains are expected for the LV and HV prototypes developed in this abstract, compared to a two-level topology as well as lower passive size.

Thermal Characterization and Design for a High Density GaN-Based Power Stage Speaker: Edward Jones, Ph.D., Senior Applications Engineer

GaN transistors offer significant reduction in operating losses and power stage footprint over conventional Si MOSFETs. With Chipscale GaN FETs, the power density can be further improved by taking advantage of six-sided cooling to extract heat from the FET case as well as through the board. Prior work has shown tremendous improvement in the current-handling capability of chipscale GaN by adding a heatsink1,2. Characterizing a thermal design with temperature sensors compromises the design’s effectiveness, particularly with smaller dies and higher power density converters. Instead, the junction temperatures can be extracted by measuring temperature-sensitive electrical parameters such as Rds,on3. This paper introduces a methodology to extract the thermal resistances of a high density GaN power stage, then presents the resulting improvement in current-handling capability.

Meet with EPC at WiPDA 2018

Visit with EPC in the exhibit area where displays highlight how eGaN FETs and ICs used in applications such as high power density DC-DC power conversion, LiDAR for autonomous vehicles, and motor drives. Stop by to meet EPC’s applications team – the leading experts in applying GaN technology.