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How To GaN: Paralleling High Speed eGaN FETS for High Current Applications

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This column evaluated the ability to parallel eGaN® FETs for higher output current applications by addressing the challenges facing paralleling high speed, low parasitic devices, and demonstrated an improved paralleling technique. For experimental verification of this design method, four parallel half bridges in an optimized layout were operated as a 48 V to 12 V, 480 W, 300 kHz, 40 A buck converter, and achieved efficiencies above 96.5%, from 35% to 100% load. The design method achieved superior electrical and thermal performance compared to conventional paralleling methods and demonstrated that high speed GaN devices can be effectively paralleled for higher current operation.

EEWeb
By: Alex Lidow
April, 2014

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