Frequently Asked Questions

eGaN® FET Characteristics

How do EPC’s enhancement mode transistors compare with power MOSFETs?

EPC’s enhancement mode GaN transistors (eGaN® FETs) are very similar to silicon power MOSFETs – except much higher performance! If you know how to use a power MOSFET, it will be easy to transition to eGaN FETs to achieve higher efficiency, higher speed, and higher power density. For a comparison in performance between the two technologies, watch the video “How to GaN 01: Introduction – Material Comparisons”.

What are the limitations on the gate input for EPC’s eGaN devices?

Care must be taken not to exceed the absolute maximum voltage rating published on the datasheet. To make is easy for the designer to avoid this problem, there are several IC’s that control the maximum voltage on the eGaN FET while providing high-speed drive capability. Go to http://epc-co.com/epc/Products/eGaNDrivers.aspx for the latest availability of driver ICs. It is also advisable to use an efficient layout that minimizes overshoot. Please watch the video “How To GaN 06: Design Basics – Layout” for additional details on layout.

How do I lay out the eGaN FETs in my high performance power conversion circuit?

Because eGaN FETs are so fast, additional care must be taken to lay out your circuit with minimum parasitic inductance. EPC has developed optimal layout techniques that can be found in the whitepaper “Optimizing PCB Layout with eGaN FETs” ) and the video “How to GaN 06: Design Basics – Layout

Does the GaN have a body diode? If so how does it compare with the Silicon MOSFETs with respect to forward voltage drop and reverse recovery characteristics?

eGaN FETs do not have a parasitic body diode like Si-FETs, but offer reverse conduction by a different mechanism. Only majority carriers are involved in GaN device conduction so there is zero reverse recovery. The forward voltage of the internal diode is higher than the diode forward drop in a silicon based FET, hence the dead time or the diode conduction time should be minimized to get maximum efficiency. In short, the body diode in eGaN FET acts like a Schottky diode with slightly higher forward drop. For further detail of the operation in this mode, please refer to “Fundamentals of Gallium Nitride Transistors”, or view the following videos:
How To GaN 01: Introduction – Material Compositions
How to GaN 02: Introduction – Performance Characteristics

How does the "body diode" forward drop change if the gate is driven to a negative voltage?

The “body diode” drop for the eGaN Device is the typical Gate Threshold Voltage. A negative voltage applied to the gate will add to the “Vf” drop of the diode – hence applying a negative gate voltage is NOT recommended if you plan to use the reverse conduction characteristic.

Unlike silicon MOSFETs, there is no need to wait for the usual dead time. In other words, since the switch turns off in less than 10 ns (typical), there is no need to wait for 40-60 ns for the other device in the same leg to shut off before turning on the channel. As with any synchronous FET application, the diode conduction needs to be kept to the minimum. Please see white paper Dead-Time Optimization for Maximum Efficiency

How do I test EPC’s enhancement mode GaN transistors?

EPC’s eGaN® FETs are very similar to silicon power MOSFETs. There are, however, a few key differences that must be understood before performing electrical tests on these high-performance devices. A guide to testing and characterizing EPC’s eGaN FETs can be found at, http://epc-co.com/epc/documents/product-training/Characterization_guide.pdf.

What is the temperature range for extended application?

The 40 V lead free eGaN FETs (EPC2014 & EPC2015) are rated at 150°C. The 100 V (EPC2001 & EPC2007) and 200 V (EPC2010 & EPC2012) are rated at 125°C. GaN transistors in general are capable of operating at temperatures as high as 300°C. EPC’s devices are mounted as flipchips in a Land Grid Array (LGA) format onto PCB’s using lead free solder. This, plus the maximum temperature allowed at the surface of a commercial PCB is typically no higher than 105°C, are the two reasons EPC has not initially rated these parts at higher temperatures.

What is the temperature dependence of Gate-Source Threshold?

The Gate-Source Threshold is essentially flat with temperature as seen in Figure 9 on datasheets. This avoids turn off difficulties at elevated temperature, and along with a positive temperature coefficient of the transfer characteristics curve, avoids current crowding during switching transitions, and in linear circuits.

Are the devices Avalanche rated?

EPC’s eGaN FETs do have an overvoltage rating. For general specifications and use of the rating go to the device datasheets.

Where can I find information on the thermal resistance of eGaN FETs?

Thermal resistance is a major factor in determining the capabilities of discrete power devices. From a device’s thermal characteristics both the maximum power dissipation and maximum current can be derived for user applications. While the thermal performance of traditional silicon MOSFETs is well understood, measuring the thermal performance of eGaN® FETs requires some further explanation. EPC has written an application note investigating the testing method and results of thermal resistance measurements on eGaN FETs. This application note can be found at http://epc-co.com/epc/documents/product-training/Characterization_guide.pdf.

Thermal resistance data can be found on the respective device datasheets; http://epc-co.com/epc/Products/eGaNFETs.aspx.

Additionally, thermal models can be found at http://epc-co.com/epc/DesignSupport/DeviceModels.aspx

What are the theoretical temp limits for eGaN devices?

GaN transistors have been demonstrated to operate successfully at temperatures as high as 300°C. Temperature ratings for released EPC products can be found in the product table at http://epc-co.com/epc/Products/eGaNFETs.aspx

How does EPC handle the “Miller Effect”?

“Miller Capacitance”, CGD, is quite low for these devices. Therefore, switching losses due to the “Miller Effect” are quite low. Handling the “Miller Effect” during a dV/dt is similar to handling it in MOSFETs. In low voltage devices, the capacitive divider between CGD and CGS is enough to keep the device off. At higher voltages, a low impedance turn off path is required to keep a device off under high dV/dt. EPC makes it easy to drive our eGaN FETs by working with IC companies to produce driver ICs that effectively manage the turn on and turn off of eGaN FETs at very high dv/dt.