项目及活动

ECCE

2018年9月24日星期一
ECCE
地点: 美国俄勒冈州波特兰市

基于氮化镓器件的开关电容式三级降压转换器,采用级联同步配置的自举式栅极驱动电路 讲者:高级应用工程师Suvankar Biswas博士

由于目前的数据中心采用的功率架构由12 V转为48 V机架,因此更关注改善48 V功率转换的效率及密度。基于氮化镓器件的三级转换器是一个高功率密度及效率的解决方案。本研讨会将分享面向48 V电源转换应用的高性能、基于氮化镓器件的开关电容式三级降压转换器。为了在多电平拓扑发挥氮化镓技术的优势,我们建议采用改善了的级联同步配置的自举技术。这种栅极驱动技术比早前基于氮化镓器件的多电平拓扑的栅极驱动技术更细小及更简单,可以实现优越的栅极电压调节。为了取得实验证明,我们比较开关电容式三级降压转换器(改善了栅极驱动电路及闭环飞跨电容平衡)和传统的降压转换器,我们看到,三级转换器减少了50%电感及25%功耗。为了进一步展示栅极驱动电路在未来有可能实现到的应用,我们构建了400 V的高压原型,它的实验结果比一般半桥式原型更为优越。此外,我们对完全不需要全额定电压开关并采用Zener二极管的一般启动保护电路进行认证。

IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA 2018)

2018年10月31日星期三 - 2018年11月2日星期五
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA 2018)
地点: Atlanta, GA

Evaluation of GaN based Multilevel Converters Speaker: Suvankar Biswas, Ph.D., Senior Applications Engineer

With the significant reduction in board space occupied by the smaller GaN transistors, topologies that require a greater number of active devices as a tradeoff for reduced passive size, the main barrier to higher density, have become attractive. Switched capacitor multilevel converters1 are good examples of topologies that can effectively reduce or eliminate passive components. Two GaN based prototypes (three-level converters), one for a low voltage (LV) 48 V server application and the other for a high voltage (HV) 400 V power factor correction (PFC) circuit are discussed in this paper. Significant efficiency gains are expected for the LV and HV prototypes developed in this abstract, compared to a two-level topology as well as lower passive size.

Thermal Characterization and Design for a High Density GaN-Based Power Stage Speaker: Edward Jones, Ph.D., Senior Applications Engineer

GaN transistors offer significant reduction in operating losses and power stage footprint over conventional Si MOSFETs. With Chipscale GaN FETs, the power density can be further improved by taking advantage of six-sided cooling to extract heat from the FET case as well as through the board. Prior work has shown tremendous improvement in the current-handling capability of chipscale GaN by adding a heatsink1,2. Characterizing a thermal design with temperature sensors compromises the design’s effectiveness, particularly with smaller dies and higher power density converters. Instead, the junction temperatures can be extracted by measuring temperature-sensitive electrical parameters such as Rds,on3. This paper introduces a methodology to extract the thermal resistances of a high density GaN power stage, then presents the resulting improvement in current-handling capability.

Meet with EPC at WiPDA 2018

Visit with EPC in the exhibit area where displays highlight how eGaN FETs and ICs used in applications such as high power density DC-DC power conversion, LiDAR for autonomous vehicles, and motor drives. Stop by to meet EPC’s applications team – the leading experts in applying GaN technology.