The intermediate bus architecture (IBA) is currently the most popular power system architecture in computing and telecommunications equipment. It typically consists of a +48 V system power distribution bus that feeds on-board isolated converters, which in turn supply power to a 12 V power bus. From the 12 V power bus, the final power is delivered to the end loads by regulated non-isolated point of load (POL) converters. In this paper we demonstrate substantial system gains using enhancement mode gallium nitride power transistors in high frequency isolated and non-isolated DC-DC converters. These transistors, also known as eGaN® FETs, have been commercially available for over three years and are making significant inroads replacing the aging silicon power MOSFET.
Distributed power systems are prevalent in telecommunications, networking, and high-end server applications and generally utilize a 48 V bus voltage adopted from the telecom industry. In the traditional distributed power architecture (DPA), from the 48 V bus voltage, a number of fully regulated isolated DC/DC point of load (POL) converters are used to deliver the required voltage and power to the individual loads. As communications, networking, and high-end server systems have become more complex, the voltages and currents demanded by the growing number of loads have increased significantly .
To simplify design and improve performance, the concept of intermediate bus architecture (IBA) has become widely accepted ,. The popular IBA approach employs a lower number of 48 V isolated bus converters to satisfy isolation requirements and supply an intermediate bus voltage which is generally 12 V. From the 12 V bus, the final power is provided to the loads by smaller, more efficient, regulated non-isolated POL converters.
To improve overall performance in the IBA, more efficient power devices are required. For silicon (Si) MOSFETs, the gains in performance have slowed as the technology has matured and approached its theoretical limits . Gallium nitride devices have emerged as a possible replacement for silicon devices in various power conversion applications and as an enabler of new applications not previously possible. GaN devices are a high electron mobility transistor (HEMT) with a higher band gap, electron mobility, and critical electric field strength than silicon . GaN technology, in its early stages, already outperforms the theoretical limits of MOSFETs in the metric of specific on resistance for a given breakdown voltage, as shown in figure 1.
Figure 1: Theoretical and current eGaN FET on-resistance vs. blocking voltage capability for silicon, silicon-carbide, and gallium nitride devices
II. Comparing Performance Metrics of GaN and Si Power Devices
A. Hard Switching Applications
The first commercially available enhancement mode gallium nitride transistors have a lateral structure with voltages ranging from 40-200 V. These HEMT transistors operate similarly to the traditional Si MOSFETs and can provide improved switching and packaging performance . While specific on resistance for a given breakdown voltage, as shown in figure 1, demonstrates the ability of GaN transistors to significantly shrink the size of the power device compared to Si counterparts, this metric does not directly correlate to in-circuit switching performance.
In a traditional hard switching transition, the switching losses are impacted primarily by two device parameters, QGD, also known as the miller charge, which controls the voltage rising (TVR) and falling speed; and QGS2, which is the portion of the gate source charge from the device threshold voltage to the gate plateau voltage, which controls the current rising and falling speed (TCF).
Figure 2: Ideal hard switching waveforms at device turn off transition
The turn off period, shown in figure 2, begins with a decrease of gate drive voltage; when the gate voltage reaches the plateau, the voltage across the device will begin to rise, being driven by the gate current, IG. During the voltage rising period, the transistor encounters both current and voltage in the device, resulting in switching loss. For the voltage rising period, the device parameter determining loss is QGD. When the transistor voltage reaches the input voltage, the current in the device will begin to fall and more switching loss in the device will be incurred. For the current falling period, the device parameter determining loss is QGS2. The power loss during the turn off switching transition can be given by:
Where VIN is the input voltage, IOFF is the device current at turn off, QGD is the miller charge, QGS2 is the gate to source charge from the device threshold voltage to plateau voltage, and IG is the gate driver current.
For the turn on switching losses, the same principles apply; minimizing the QGD and QGS2 parameters will decrease switching losses incurred in a hard switching application. The turn on loss is given by:
Where ION is the device current at turn on.
Switching figure of merit (FOM) - is used to compare the in circuit performance capability of a given device technology in different applications. In hard switching applications for the voltage and current ranges of eGaN FETs (40- 200 V) a useful figure of merit is derived to minimize the power loss contributed from the device conduction and switching losses which are given by:
Where IRMS is the RMS current conducted through the device, RDSON is the on-resistance of the device, IOUT is the output current, FSW is the switching frequency, QGD_SP and QGS 2_SP are the specific charges, and RDSON_SP is the specific on-resistance for a given device area, ADEVICE.
To determine the device parameters producing minimum losses, the derivative of (7) is taken with respect to ADEVICE with dPLOSS/dADEVICE set to zero. The optimal value of ADEVICE is then determined, yielding the optimal die size, AOPTIMAL.
Placing (8) into (7) yields the minimal power loss in terms of device parameters and circuit operating conditions.
Combining the device related parameters contributing to loss, a figure of merit to simply compare the in circuit performance capability of different device technologies can be given as:
For a given technology, a lower value of FOM will be able to reduce the power loss proportional to:
In this equation PLOSS is the power loss contributed from the device conduction and switching losses.
The comparison of the hard switching FOM for a 100 V eGaN FET and 80 V MOSFET devices is shown in figure 3, the eGaN FET has a 70% lower FOM than the best state of the art lower rated Si devices. For a 48 V converter, this translates to a device power loss reduction of almost a factor of two in hard switching applications by replacing Si MOSFETs with eGaN FETs.
Figure 3: Hard switching figure of merit comparison for 100 V eGaN
FET and 80 V MOSFETs (VDS=0.5·device voltage rating, IDS=15 A)
B. Soft Switching Applications
In soft switching applications the switching related losses are minimized by using techniques such as zero voltage switching (ZVS) and zero current switching (ZCS). With the reduction of switching losses, the QGD and QGS2 terms that dominated losses in hard switching applications are no longer the critical device parameters determining circuit performance.
There are many different soft switching techniques and directly deriving an analytical FOM to minimize loss for the wide variety of soft switching methods into a simple metric to compare device technologies is not practical. In most soft switching applications the device output charge, QOSS, has a large impact on performance as it directly impacts the energy required to achieve ZVS. A reduction in energy required to achieve ZVS can result in reduced dead times and ZVS currents, providing both a larger power delivery period and lower RMS currents in a high frequency soft switching converter. Similarly, QOSS is also the main loss component in ZCS switching. The other major contributor to loss is the gate charge, QG, which is a major switching related loss in high frequency soft switching applications.
To compare the critical parameters that influence the in-circuit performance of different device technologies in soft switching applications, a figure of merit is proposed:
Where QOSS is the output charge of the device and QG is the gate charge of the device.
The comparison of soft switching FOM for a 100 V eGaN FET and 100 V and 80 V MOSFET devices is shown in figure 4. The eGaN FET offers over a 60% reduction in FOM compared to the best state of the art 100 V Si MOSFET, and around a 50% reduction over the best 80 V Si MOSFET. The significant reduction in soft switching figure of merit offered by GaN technology enables significant performance improvements in high frequency soft switching applications. The benefits of replacing a Si MOSFET with an eGaN FET in a high frequency resonant converter will be verified in the following section.
Figure 4: Soft switching figure of merit comparison for 100 V eGaN FET and 80 V MOSFETs (VDS=0.5·device voltage rating, IDS=15 A
III. eGaN FETs in Resonant Isolated DC-DC Converters
To achieve improved efficiency at higher switching frequencies, resonant topologies may be considered. Resonant topologies are particularly beneficial in DC/DC transformer applications, also known as a DCX, or an unregulated bus converter due to the removal of the regulation requirements, allowing the converter to always operate at the resonant frequency. In a 48 V IBA, the final regulation to the loads is provided by smaller, more efficient, regulated non-isolated POL converters. This allows the bus converters to be operated as unregulated DC/DC transformers, improving efficiency and simplifying converter design -.
To demonstrate the opportunities enabled by converting from silicon-based power MOSFETs to enhancement mode GaN devices in soft switching applications, we chose the topology as shown in Figure 5 that employed a resonant technique utilizing the transformer’s magnetizing inductance (LM) and resonance of the leakage inductance (LK), together with a small output capacitance (CO), to achieve zero voltage switching, limit turn-off current, and eliminate body diode conduction , .
Figure 5: High frequency bus converter (a) Schematic (b) Operating waveforms
To obtain a direct comparison in performance between GaN devices and Si MOSFETs in an isolated converter, having identical layouts and using the same topology is critical. Isolated DC-DC converter performance is heavily dependent on topology selection, printed circuit board (PCB) layout, number of PCB inner layers, copper weight of inner layers, and the design of the transformer. To accurately compare the performance of GaN and Si in a high frequency resonant bus converter application, devices with similar on-resistance were selected, the same circuit topology was used, and a similar layout was maintained for both designs.
Two experimental prototypes, shown in figure 6, were designed and tested based on the schematic in figure 5(a) to run at a switching frequency of 1.2 MHz. Both PCBs were constructed with 12 layers and two ounce copper thickness for all layers. To accurately compare only device performance, these prototypes both had the same 3F45 Mn-Zn transformer core and identical windings designed from . The placement of the primary side input capacitors and secondary resonant capacitors were similar for both designs to ensure similar parasitic inductances for the primary and secondary loops, with the only differences being those introduced by the different packages of the Si MOSFETs and eGaN FETs. By using eGaN FETs with lower specific on resistance and improved packaging, the active footprint area shrank significantly, reducing the power stage size by 30% compared to the Si MOSFET benchmark design.
Figure 6: Experimental 48 V to 12 V bus converter prototypes operating at a switching frequency of 1.2 MHz constructed with (a) silicon MOSFETs, and (b) gallium nitride eGaN FETs
The experimental switching waveforms for the designs at 1.2 MHz are shown in Figure 7. Both designs have the same magnetizing inductance built into the transformer via an air gap to achieve zero-voltage switching during the device off state. Due to almost a factor of 2 decrease in output charge provided by the primary and secondary eGaN FETs, the ZVS transition is achieved in a proportionally shorter period, increasing the effective duty cycle and improving the overall converter performance. For the Si MOSFET design, the dead time required for ZVS was measured to be 87 ns and the effective duty cycle for each device was limited to 34%. With the faster switching eGaN FETs, the dead time was reduced to 42 ns resulting in a 42% duty cycle for each device while allowing for an extended power delivery period. From the switching waveforms, it can also be seen that the gate drive speed for the eGaN FET is significantly faster than the Si MOSFET counterpart even when driven with a lower gate drive voltage, providing both faster switching speed and reduced gate losses.
Figure 7: Switching waveforms showing effective duty cycle for primary side eGaN FET and Si MOSFET designs at FS = 1.2 MHz, VIN = 48 V, and IOUT = 26 A, eGaN FET: EPC2001, MOSFET: BSC057N08NS3.
The comparison in efficiency between the two designs operating at 1.2 MHz is shown in Figure 8. The eGaN FET-based converter offers a one-percentage point improvement in peak efficiency over its Si MOSFET counterpart, resulting in about 25% less power loss. Since products based on this type of design are thermally limited, the reduction in power loss translates directly into higher output power handling capability. In this case, the eGaN FET converter can increase the output power capability by up to 65 W while maintaining the same total converter loss when compared to the benchmark Si MOSFET design. Assuming an approximate 12 W maximum power loss for both designs, the output power of the eGaN FET-based converter can be increased from 270 W to 325 W.
Figure 8: Experimental comparison between eGaN FET and Si MOSFET based VIN = 48 V, VOUT = 12 V, FSW = 1.2 MHz resonant bus converters.
IV. eGaN FETs in Non-Isolated DC-DC Converters
The limited and ever decreasing motherboard area around computer processors that are available for power conversion has driven the need for ever decreasing size in point of load (POL) modules. Since the size of the magnetic components dominates the converter volume, frequencies are pushed higher to reduce magnetic volume, reducing efficiency and increasing power loss. Improvements in device hard switching performance can be directly translated into smaller power modules.
Figure 9: Hard switching figure of merit comparison for 40 V eGaN
FET and 40 V MOSFETs (VDS=0.5·Device voltage rating, IDS=20 A)
From a hard switching FOM comparison, shown in figure 9, eGaN FETs can offer higher efficiency than 40 V Si MOSFET counterparts. In practical hard switching applications, FOM is just one of the contributors to achieving higher efficiency. To enable the high switching speed available from low FOM, low parasitic packaging and PCB layout is required. eGaN FETs were developed in land grid array (LGA) packages that not only have low internal inductance, but enable the user to design ultra-low inductance into their board. The PCB layout contributes to both the common source inductance (LS), and the high frequency power commutation loop inductance (LLOOP), shown in figure 10a. These parasitics greatly impact the loss of a converter, as shown in figure 10b. At EPC, we have developed an optimal layout  further enhancing the benefits of eGaN FET technology, providing additional efficiency gains and higher voltage operation capability.
Figure 10: (a) Synchronous buck converter with parasitic inductances
(b) Parasitic inductance impact on power loss (VIN=12 V, VOUT=1.2 V, IOUT=20 A, FSW=1 MHz, Top Switch: EPC2015, Synchronous Rectifier: EPC2015)
The efficiency comparison of buck converters operating at a 1 MHz switching frequency using state of the art 40 V Si MOSFETs and 40 V eGaN FETs is shown in figure 11a, the eGaN FET based design can improve efficiency over 3% when compared to the Si MOSFET. With the significantly reduced high frequency loop inductance provided by the ultra-low package inductance of the eGaN FET package in combination with an eGaN FET optimized PCB layout, a 500% increase in switching speed and a 40% reduction in voltage overshoot, as shown in figure 11b, can be achieved compared to the 40 V Si MOSFET benchmark.
Figure 11: (a) Efficiency comparison and (b) Switching node waveforms (IOUT=20 A) of eGaN FET and MOSFET designs (VIN=12 V, VOUT=1.2 V, Fs=1 MHz, L=300 nH, eGaN FETS: T: EPC2015 SR: EPC2015, MOSFETs: T: BSZ097N04LSG SR: BSZ040N04LS G)
The availability of high performance eGaN FETs offers the potential to switch at higher frequencies and higher efficiency than possible with traditional Si MOSFET technology. eGaN FETs have a distinct advantage over silicon MOSFETs in both hard and soft switching applications. In this work, two figures of merits were proposed to compare device technologies for use in hard and soft switching applications.
The benefits of eGaN FETs in an IBA system with a 48 V isolated resonant bus converter first stage operating at 1.2 MHz and a 12 V non-isolated hard switching POL second stage operating at 1 MHz were demonstrated. By replacing silicon MOSFETs with eGaN FETs, the losses were reduced over 20% in both the isolated and non-isolated stages, providing superior system performance not achievable with Si technology. No matter what the application, gallium nitride technology offers the potential to improve performance and as this technology matures these benefits will only increase.
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