Sign up today to get the latest news and updates from EPC on new product announcements, applications work, and much more. Sign up for EPC email updates or text "EPC" to 22828.
Enhancement-mode gallium nitride (eGaN) FETs have demonstrated excellent thermomechanical reliability in actual operation in the field or when tested according to AEC or JEDEC standards. This is because of the inherent simplicity of the “package,” the lack of wire bonds, dissimilar materials, or mold compound. Recently, an extensive study of underfill products was conducted to experimentally generate lifetime predictions. A finite element analysis at the end of this section explains the experimental results and generates guidelines for selection of underfill based on key material properties.
This article discusses the challenges that thermal management raises due to increase power density, especially with chip-scale packaging (CSP). What is sometimes overlooked, however, is that CSP eGaN® power FETs and integrated circuits have excellent thermal performance when mounted on standard printed circuit board (PCBs) with simple methods for attaching heat sinks. Simulations, supported by experimental verification, examine the effect of various parameters and heat flow paths to provide guidance on designing for performance versus cost.
Bodo’s Power Systems
eGaN FETs and ICs enable very high-density power converter design, owing to their compact size, ultra-fast switching, and low on-resistance. The limiting factor for output power in most high-density converters is junction temperature, which prompts the need for more effective thermal design. The chip-scale packaging of eGaN FETs and ICs offer six-sided cooling, with effective heat extraction from the bottom, top, and sides of the die. This article presents a high-performance thermal solution to extend the output current capability of eGaN-based converters.
Best design practices utilize the advantages offered by eGaN FETs, including printed circuit board (PCB) layout and thermal management. As GaN transistor switching charges continue to decrease, system parasitics must also be reduced to achieve maximum switching speeds and minimize parasitic ringing typical of power converters.