Written by Michael de Rooij and Alana Nakata - Efficient Power Conversion
Published in: PCIM Europe 2017; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management; Proceedings of
eGaN FETs, which are available in non-traditional chip scale packages (CSP) as land grid array (LGA) and/or ball grid array (BGA) formats, have repeatedly demonstrated higher power density and higher efficiency performance than equivalent MOSFETs across various applications [1, 2]. Those improvements are contingent upon proper layout practices documented extensively in [1, 3] that minimize unwanted parasitic elements. Over the seven years since eGaN FETs were first launched into the market there have been a total of 127 device failures out of a total of more than 17 billion hours in actual use in the field, 75 of which were a result of poor assembly technique or poor printed circuit board (PCB) design practices . Designers are becoming more familiar with the PCB design rules that affect manufacturability and are less forgiving compared to MOSFETs due to their relatively smaller sizes. This paper will cover the various guidelines for PCB design that maximize the performance of eGaN FETs and reliability yet still rely on existing PCB manufacturing capabilities.