GaN Talk a blog dedicated to crushing silicon
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New 200 V eGaN Devices Double the Performance Edge Over the Aging Silicon Power MOSFET.

New 200 V eGaN Devices Double the Performance Edge Over the Aging Silicon Power MOSFET.
Aug 21 2020

Efficient Power Conversion (EPC) is doubling the performance distance between the aging silicon power MOSFET and eGaN® transistors with 200 V ratings.  The new fifth-generation devices are about half the size of the prior generation.  This performance boost comes from two main design differences, as shown in figure 1.  On the left is a cross-section of the fourth generation 200 V enhancement-mode GaN-on-Si process.  The cross-section on the right is the fifth-generation structure with reduced distance between gate and source electrodes and an added thick metal layer. These improvements, plus many others not shown, have doubled the performance of the new-generation FETs.

ePower™ Stage – Redefining Power Conversion

ePower™ Stage – Redefining Power Conversion
Mar 16 2020

Beyond just performance and cost improvement, the most significant opportunity for GaN technology to impact the power conversion market comes from its intrinsic ability to integrate multiple devices on the same substrate. GaN technology, as opposed to standard silicon IC technology, allows designers to implement monolithic power systems on a single chip in a more straightforward and cost-effective way.

Today, the most common building block used in power conversion is the half bridge. In 2014, EPC introduced a family of integrated half-bridge devices which became the starting point for the journey towards a power system-on-a-chip. This trend was expanded with the introduction of the EPC2107 and EPC2108, which integrated half bridges with integrated synchronous bootstrap. In 2018 we further continued the integration path with the introduction of eGaN ICs combining gate drivers with high-frequency GaN FETs in a single chip for improved efficiency, reduced size, and lower cost. Now, the ePower™ Stage IC family redefines power conversion by integrating all functions in a single GaN-on-Si integrated circuit at higher voltages and higher frequency levels beyond the reach of silicon.

How to Design an eGaN FET-Based Power Stage with an Optimal Layout

How to Design an eGaN FET-Based Power Stage with an Optimal Layout
Oct 24 2018

Motivation

eGaN FETs are capable of switching much faster than Si MOSFETs, requiring more careful consideration of PCB layout design to minimize parasitic inductances. Parasitic inductances cause higher overshoot voltages and slower switching transitions. This application note reviews the key steps to design an optimal power stage layout with eGaN FETs, to avoid these unwanted effects and maximize the converter performance.

Impact of parasitic inductance on switching behavior

As shown in figure 1, three parasitic inductances can limit switching performance 1) power loop inductance (Lloop), 2) gate loop inductance (Lg), and 3) common-source inductance (Ls). The chip-scale package of eGaN FETs eliminates any significant inductance within the transistor itself, leaving the printed circuit board (PCB) as the main contributor. Each parasitic inductance is a consequence of the total area encompassed by the dynamic current path and its return loop. (See WP009: Impact of Parasitics on Performance).