GaN Talk a blog dedicated to crushing silicon
Term: DC-DCコンバータ
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Building the Smallest, Most Cost Effective, Highest Efficiency Non-isolated 48 V to 5 - 12 V DC to DC Converters using latest Generation 100 V eGaN FETs

Building the Smallest, Most Cost Effective, Highest Efficiency Non-isolated 48 V to 5 - 12 V DC to DC Converters using latest Generation 100 V eGaN FETs
Apr 24 2019

The latest generation of 100 V GaN devices increase the efficiency, shrink the size, and reduce system cost for 48 V power conversion. The EPC2045, shown in figure 1, is rated at 100 V with 7 mΩ on- resistance that can carry a continuous current of 16 A. The EPC2045 is nearly one-tenth the footprint of a comparable Si MOSFET and has lower parasitic capacitances and can switch much faster than equivalent silicon devices, yielding lower switching loss even at higher switching frequency.

The EPC2053, shown in figure 2, is rated at 100 V with 4 mΩ on-resistance that can carry a continuous current of 32 A. The EPC2053 has lower parasitic capacitances and on-resistance than its silicon counterparts, yielding faster switching speed and lower power losses even at higher switching frequencies. These characteristics enable increasing the output power while shrinking the volume of the converter.

Exceeding 98% Efficiency in a Compact 48 V to 12 V, 900 W LLC Resonant Converter Using eGaN FETs

Exceeding 98% Efficiency in a Compact 48 V to 12 V, 900 W LLC Resonant Converter Using eGaN FETs
Apr 03 2019

Motivation

The rapid expansion of the computing and telecommunication market is demanding an ever more compact, efficient and high power density solution for intermediate bus converters. The LLC resonant converter is a remarkable candidate to provide a high power density and high-efficiency solution. eGaN® FETs with their ultra-low on-resistance and parasitic capacitances, benefit LLC resonant converters by significant loss reduction that is challenging when using Si MOSFETs. A 48 V to 12 V, 900 W, 1 MHz LLC DC to DC transformer (DCX) converter employing eGaN FETs such as EPC2053 and EPC2024 is demonstrated, yielding a peak efficiency of 98.4% and a power density exceeding 1500 W/in3.

How to Design an eGaN FET-Based Power Stage with an Optimal Layout

How to Design an eGaN FET-Based Power Stage with an Optimal Layout
Oct 24 2018

Motivation

eGaN FETs are capable of switching much faster than Si MOSFETs, requiring more careful consideration of PCB layout design to minimize parasitic inductances. Parasitic inductances cause higher overshoot voltages and slower switching transitions. This application note reviews the key steps to design an optimal power stage layout with eGaN FETs, to avoid these unwanted effects and maximize the converter performance.

Impact of parasitic inductance on switching behavior

As shown in figure 1, three parasitic inductances can limit switching performance 1) power loop inductance (Lloop), 2) gate loop inductance (Lg), and 3) common-source inductance (Ls). The chip-scale package of eGaN FETs eliminates any significant inductance within the transistor itself, leaving the printed circuit board (PCB) as the main contributor. Each parasitic inductance is a consequence of the total area encompassed by the dynamic current path and its return loop. (See WP009: Impact of Parasitics on Performance).