GaN Talk a blog dedicated to crushing silicon
Term: オープンコンピュートプロジェクト
2 post(s) found

GaN Rising as Power Chain Option as Energy Demand, Cost Grows

GaN Rising as Power Chain Option as Energy Demand, Cost Grows
Nov 29 2018

This post was originally published by Bill Kleyman on November 5, 2018 on the Data Center Frontier  web site. Learn more about eGaN technology and EPC GaN solutions for the Data Center.

The data center is an ever-changing entity and part of our technological landscape. But sometimes the biggest changes in the colocation industry happen at the core of what makes a data center tick, and may not be visible at first glance. In this instance, we’re talking about data center power, and the potential of creative solutions on the market, such as using Gallium nitride (GaN) in power conversion equipment.

How to Design an eGaN FET-Based Power Stage with an Optimal Layout

How to Design an eGaN FET-Based Power Stage with an Optimal Layout
Oct 24 2018

Motivation

eGaN FETs are capable of switching much faster than Si MOSFETs, requiring more careful consideration of PCB layout design to minimize parasitic inductances. Parasitic inductances cause higher overshoot voltages and slower switching transitions. This application note reviews the key steps to design an optimal power stage layout with eGaN FETs, to avoid these unwanted effects and maximize the converter performance.

Impact of parasitic inductance on switching behavior

As shown in figure 1, three parasitic inductances can limit switching performance 1) power loop inductance (Lloop), 2) gate loop inductance (Lg), and 3) common-source inductance (Ls). The chip-scale package of eGaN FETs eliminates any significant inductance within the transistor itself, leaving the printed circuit board (PCB) as the main contributor. Each parasitic inductance is a consequence of the total area encompassed by the dynamic current path and its return loop. (See WP009: Impact of Parasitics on Performance).