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Oct 24, 2018

How to Design an eGaN FET-Based Power Stage with an Optimal Layout

Rick Pierson, Senior Manager, Digital Marketing


eGaN FETs are capable of switching much faster than Si MOSFETs, requiring more careful consideration of PCB layout design to minimize parasitic inductances. Parasitic inductances cause higher overshoot voltages and slower switching transitions. This application note reviews the key steps to design an optimal power stage layout with eGaN FETs, to avoid these unwanted effects and maximize the converter performance.

Impact of parasitic inductance on switching behavior

As shown in figure 1, three parasitic inductances can limit switching performance 1) power loop inductance (Lloop), 2) gate loop inductance (Lg), and 3) common-source inductance (Ls). The chip-scale package of eGaN FETs eliminates any significant inductance within the transistor itself, leaving the printed circuit board (PCB) as the main contributor. Each parasitic inductance is a consequence of the total area encompassed by the dynamic current path and its return loop. (See WP009: Impact of Parasitics on Performance).