Designs, implements, and verifies mask layouts of Analog ICs and discrete power transistors in GaN process technologies, from concept to successful tape out.
- Mask layout design at both individual die and reticle levels.
- DRC, ERC, LVS, PEX, and debugging of layouts.
- Translate schematics into physical layout, manually and with schematic driven layout (SDL) tools.
- Proficient with analog layout techniques that include use of common-centroid and interleaving of devices for device matching.
- In addition to new designs, will revise and debug existing layouts.
- Understand, interpret, and accurately apply Design Rule and Electrical Rule Manuals.
- Accurate, precise execution of layouts in new emerging technology, when EDA tools and methods are rapidly changing.
- Detailed, accurate, and organized documentation of layouts in Microsoft Excel and/or Word, as needed.
- Works under guidance of multiple circuit designer and device engineers on separate layout projects.
- Self driven and motivated to achieve schedules and commitments.
- Participates in design reviews.
- May write Mask Tooling/Order forms.
- Scripting skills are a Plus, but not required.