常见问题

EPC’s enhancement mode GaN transistors (eGaN^® FETs) are very similar to silicon power MOSFETs – except much higher performance! If you know how to use a power MOSFET, it will be easy to transition to eGaN FETs to achieve higher efficiency, higher speed, and higher power density. For a comparison in performance between the two technologies, watch the video “How to GaN 01: Introduction – Material Comparisons”.

Care must be taken not to exceed the absolute maximum voltage rating published on the datasheet. To make is easy for the designer to avoid this problem, there are several IC’s that control the maximum voltage on the eGaN FET while providing high-speed drive capability. Se the product page for a list of list of GaN-compatible ICs. It is also advisable to use an efficient layout that minimizes overshoot. Please watch the video “How To GaN 05: Design Basics – Layout” for additional details on layout.

Because eGaN FETs and ICs are so fast, additional care must be taken to lay out your circuit with minimum parasitic inductance. EPC has developed optimal layout techniques that can be found in the whitepaper “Optimizing PCB Layout with eGaN FETs” ) and the video “How to GaN 05: Design Basics – Layout”

eGaN FETs do not have a parasitic body diode like Si-FETs, but offer reverse conduction by a different mechanism. Only majority carriers are involved in GaN device conduction so there is zero reverse recovery. The forward voltage of the internal diode is higher than the diode forward drop in a silicon based FET, hence the dead time or the diode conduction time should be minimized to get maximum efficiency. In short, the body diode in eGaN FET acts like a Schottky diode with slightly higher forward drop. For further detail of the operation in this mode, please refer to eGaN FET Electrical Characteristics, or view the following videos:
How To GaN 01: Introduction – Material Compositions
How to GaN 03: Introduction – Performance Characteristics

The “body diode” drop for the eGaN Device is the typical Gate Threshold Voltage. A negative voltage applied to the gate will add to the “V_f” drop of the diode – hence applying a negative gate voltage is NOT recommended if you plan to use the reverse conduction characteristic.

Unlike silicon MOSFETs, there is no need to wait for the usual dead time. In other words, since the switch turns off in less than 10 ns (typical), there is no need to wait for 40-60 ns for the other device in the same leg to shut off before turning on the channel. As with any synchronous FET application, the diode conduction needs to be kept to the minimum. Please see white paper Dead-Time Optimization for Maximum Efficiency

EPC’s eGaN^® FETs are very similar to silicon power MOSFETs. There are, however, a few key differences that must be understood before performing electrical tests on these high-performance devices. Please refer to the guide EPC GaN Transistor Parametric Characterization Guide for more information.

EPC’s product family have maximum operating temperature ratings at 150^°C. GaN transistors in general are capable of operating at temperatures as high as 300°C. EPC’s devices are mounted as flipchips in a chip-scale package format onto PCB’s using lead free solder. This, plus the maximum temperature allowed at the surface of a commercial PCB is typically no higher than 105°C, are the two reasons EPC has not initially rated these parts at higher temperatures.

The Gate-Source Threshold is essentially flat with temperature as seen in Figure 9 on datasheets. This avoids turn off difficulties at elevated temperature, and along with a slightly negative temperature coefficient of the transfer characteristics curve, avoids current crowding during switching transitions, and in linear circuits.

EPC’s eGaN FETs and ICs do have an overvoltage rating. For general specifications and use of the rating go to the device datasheets.

Thermal resistance is a major factor in determining the capabilities of discrete power devices. From a device’s thermal characteristics both the maximum power dissipation and maximum current can be derived for user applications. While the thermal performance of traditional silicon MOSFETs is well understood, measuring the thermal performance of eGaN^® FETs and ICs requires some further explanation. EPC has written the following application note investigating the testing method and results of thermal resistance measurements on eGaN FETs, EPC GaN Transistor Parametric Characterization Guide. Thermal resistance data can be found on the respective device datasheets on the  parameteric selector guide

Additionally, thermal models can be found on the device models page.

GaN transistors have been demonstrated to operate successfully at temperatures as high as 300^°C. Temperature ratings for released EPC products can be found in the eGaN FETs and ICs product page.

“Miller Capacitance”, C_GD, is quite low for these devices. Therefore, switching losses due to the “Miller Effect” are quite low. Handling the “Miller Effect” during a dv/dt is similar to handling it in MOSFETs. In low voltage devices, the capacitive divider between C_GD and C_GS is enough to keep the device off. At higher voltages, a low impedance turn off path is required to keep a device off under high dv/dt. EPC makes it easy to drive our eGaN FETs by working with IC companies to produce driver ICs that effectively manage the turn on and turn off of eGaN FETs at very high dv/dt.

Yes, you should not attach the heat sink directly onto the top of the device. On many devices, the top is substrate and is at the same potential of the source of the device. On older generation devices it is recommended to connect the substrate pin to source. Therefore, EPC recommends the use of an insulating thermal interface material such a Liquid Gap Filler, soft thermal pad or a Putty material when attaching a heat sink. For more details, see How To Application Note 012: How to Get More Power Out of a High-Density eGaN-Based Converter with a Heatsink

On many devices the back (top) of the device (the Si substrate) is at the same potential of the source terminal. On older generation devices it is recommended to connect the substrate pin to source. Therefore, regardless of device generation the back (top) of the device should be treated as an active terminal.