Six Reasons to Rethink Power Semiconductor Packaging
6月 08, 2016
In my 40 years’ experience in power semiconductors I have visited thousands of customers, big and small, on every continent except Antarctica. When the issue invariably turns to the packaging of the power semiconductor – transistor, diode, or integrated circuit – the requests for improvement fall into six categories:
- Can you make the package smaller?
- Can you reduce the package inductance?
- Can you make the product with lower conduction losses?
- Can you make the package more thermally efficient?
- Can you sell the product at a lower price?
- Can you make the package more reliable?
eGaN® FETs and integrated circuits from EPC have taken a very different approach to packaging power semiconductors – we have ditched the package altogether!
The reason for ditching the package in the first place was serendipitous. As a fledgling startup, no company specializing in power semiconductor packaging wanted to be bothered with small volumes and high up-front engineering costs. So we went with the idea of supplying our products in chip-scale formats.
Figure 1 shows an EPC1001 transistor first introduced in March 2010. This device has a thin layer of gallium nitride (GaN) grown on top of a standard silicon substrate. Inside the GaN we fabricated a first-generation discrete transistor that performed 5 – 50 times better than the best silicon MOSFETs, depending upon the application. And, instead of a plastic molded package, we put “solderable bars” directly on the surface of the device. Flip this part over and it can be mounted it directly onto a PCB (See figure 2).
Figure 1: The EPC1001 was first introduced in March 2010 and began the chip-scale packaging revolution.
Figure 2: Two EPC eGaN FETs are soldered to a PCB. The back surface is silicon.
GaN-on-silicon has some amazing advantages over silicon power MOSFETs. In addition to much, much superior device performance, the thin layer of GaN in which the active devices are manufactured can be sealed under multiple layers of glass during the standard fabrication process. These layers of glass effectively protect the device from the environment, something silicon MOSFETs cannot do easily because the entire silicon-on-silicon structure is electrically active. The lateral GaN devices are only active on the surface attached to the PCB.
When I was CEO of International Rectifier Corporation (now part of Infineon), we built about 1 billion MOSFETs every 6 weeks. When all the expenses were added up, the cost of the packaging was equal to the cost of making the silicon chip inside the package. The smaller the device, the higher the ratio of package-to-device cost. Cutting out the packaging therefore cut out half the cost as well as a lot of the logistics required in the assembly process. This significant cost reduction was a pretty good motivator to keep going with the chip-scale packaging idea.
GaN transistors are much smaller than their silicon counterparts. This size advantage translates into additional cost benefits to the producers, translating into additional cost benefits to the user. PCB real estate is very expensive. Smaller devices mean less real estate. In some cases, the smaller footprint and greater performance of GaN enables a new end product not possible with larger silicon parts. Figure 3 is my personal favorite example of the power of “small size.” In this figure is a miniaturized X-ray machine in a pill that you swallow. The result: the X-ray pill performs a colonoscopy without prior purging. The high-resolution images of the colon are wirelessly transmitted to a receiver worn as a patch on the patient’s back. The cost of the pill is low enough that it does not have to be recovered after use (Whew!). Can’t do it with silicon; just can’t.
Figure 3: This X-ray pill from Check Cap can do a full colonoscopy without prior purging. A high resolution image of the colon is beamed wirelessly to a receiver worn as a patch on the patient’s back.
Small has other advantages. Small devices can be located closer to other devices in a circuit. This reduces unwanted inductance. Stray or parasitic Inductance is the enemy of a power system in that it causes the circuit to react more slowly and “ring” with voltage and current oscillations. This ringing can damage devices in the circuit and cause unwanted noise that may need to be filtered out.
Figure 4 shows the impact of just the inductance inside the common silicon MOSFET packages on the power losses in a common power supply. In this case, the internal package inductance causes the devices to turn on and off slower and therefore the transistor generates higher switching losses. The popular SO8 package induces losses that amount to 80% of the total losses incurred in the device. Even the most efficient package – the DirectFET – doubles the losses in the device. The EPC2001C chip-scale device has less than 20% losses added due to inductance in the traces on the PCB under the device. Lower losses, less heat, higher power conversion efficiency. Oh, and the chip-scale package also doesn’t add any unwanted resistance to the device. Package resistance can add 20-50% to the resistance of a low voltage state-of-the-art silicon MOSFET. Pure loss.
Figure 4: Popular power packages such as the SO-8, LFPAK, and DirectFET add considerable parasitic inductance to a power conversion circuit. This inductance induces large losses in the transistor inside the package.
Many customers, when they see the tiny eGaN transistors or ICs, worry about their ability to remove the heat from the part. Power losses in the transistor generate heat. Thus, this heat must be removed or the device, and the entire system, may overheat. The best way to get rid of heat is not to generate it in the first place. In the above paragraphs we explained that GaN-on-silicon devices are much more efficient than silicon-based devices and therefore generate less power losses and less heat.
However, an amazing attribute of a package-less device is that it is much more thermally efficient than a MOSFET in the best power package. Figure 5 is a comparison between eGaN FETs, double-sided QFNs, and DirectFETs. In the figure, the vertical axis is the thermal resistance from the device to the ambient and the horizontal axis is the device size. The lower the resistance the better, and eGaN FETs in chip-scale “packages” are much better. It is not a surprise, because eliminating all barriers between the active device and the ambient environment gives heat the most direct path to the outside world.
Figure 5: Chip-scale packages have lower thermal resistance than the most efficient silicon packages. Size, inductance, conduction losses, thermal resistance, and cost – chip scale beats packages every time!
What about reliability?
Experienced users and producers of power semiconductors will all tell you that it is the package that causes the most reliability problems. Packaging induces high stress on the silicon device during the encapsulation processes. Multiple dissimilar materials are used to create a protected and sealed environment, but these dissimilar materials tend to grind against each other and come apart during thermo-mechanical stress.
Over 6 years and 17 billion device hours, eGaN FETs and ICs from EPC have demonstrated an unprecedented record of reliability in the field. Whether it be in truck headlamps, on board autonomous vehicles, inside 4G/LTE base stations, or within DC-DC power supplies, eGaN FETs have demonstrated a total field failure rate of under 1 FIT (Failures every billion device hours). Figure 6 is a year-by-year record of eGaN FET field reliability.
Figure 6: Field reliability results for eGaN FETs. As of January 2016, EPC has documented over 17 billion hours in the field.
The six key attributes of a better package, size, inductance, resistance, thermal efficiency, cost, and reliability all point to the future of packaging for GaN FETs and ICs as being – package-less that is, no package at all!