* (C) Copyright Efficient Power Conversion Corporation. All rights reserved. ***************************************************************************** * Version History: * 1.00: 03/31/2022 - Initial Model Creation * 1.01: 04/12/2022 - Corrected error in parasitic resistance temperature dependence, updated * syntax for voltage-dependent capacitances .subckt EPC2050 gatein drainin sourcein .param si={aWg} so={aWg} sr={aWg} .param aWg={Wg*1E-3} Wg=172000 A1={2.996e-02*aWg} k2=2.329e+00 k3=9.000e-02 rpara=4.816e-02 + rpara_s_factor=1.049e-01 aITc=5.600e-03 arTc=-7.028e-03 k2Tc=7.091e-04 + x0_0=4.103e+00 x0_0_TC=-3.906e-03 x0_1=-9.802e-02 x0_1_TC=-6.449e-02 + dgs1=4.3e-07 dgs2=2.6e-13 dgs3=0.8 dgs4=0.23 + ags1={2.340e-12*si} ags2={9.400e-13*si} ags3=1.766e+00 ags4=1.429e-01 + ags5={0.000e+00*si} ags6=7.480e+01 ags7=1.055e+01 + agd1={1.940e-15*sr} agd2={8.190e-14*sr} agd3=-7.778e+00 agd4=1.558e+00 + agd5={1.360e-14*sr} agd6=-3.308e+01 agd7=1.720e+01 agd8={0.000e+00*sr} + agd9=-3.326e+01 agd10=8.900e-01 + asd1={3.640e-13*so} asd2={1.090e-12*so} asd3=-1.035e+01 asd4=7.580e-01 + asd5={7.000e-13*so} asd6=-1.000e+01 asd7=6.750e+01 asd8={2.250e-13*so} + asd9=-4.000e+01 asd10=2.000e+00 asd11={1.500e-13*so} asd12=-2.850e+02 asd13=1.500e+01 + rg_value=0.5 .model rpar res(TC1={-1.0*arTc} T_measured=25) rd drainin drain rpar {(1-rpara_s_factor)*rpara} rs sourcein source rpar {rpara_s_factor*rpara} rg gatein gate {(rg_value)} *Large resistors to aid convergence Rcsdconv drain source {100000Meg/aWg} Rcgsconv gate source {100000Meg/aWg} Rcgdconv gate drain {100000Meg/aWg} gswitch drain source Value {if(v(drain,source)>0, + (A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,source)-(k2*(1-k2Tc*(Temp-25))))/k3))* + v(drain,source)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,source))*v(drain,source)) ), + (-A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,drain)-(k2*(1-k2Tc*(Temp-25))))/k3))* + v(source,drain)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,drain))*v(source,drain)) ) )} ggsdiode gate source Value {if( v(gate,source) < 10, + 0.125*aWg/1077*(dgs1*(exp((v(gate,source))/dgs3)-1)+dgs2*(exp((v(gate,source))/dgs4)-1)), + 0.125*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) } ggddiode gate drain Value {if( v(gate,drain) < 10, + 0.125*aWg/1077*(dgs1*(exp((v(gate,drain))/dgs3)-1)+dgs2*(exp((v(gate,drain))/dgs4)-1)), + 0.125*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) } *Gate-source capacitance C_GS gate source {ags1} TC=0,0 gC_CGS1 gate source Q={(0.5*ags2*ags4*log(1+exp((v(gate,source)-ags3)/ags4))+ + ags5*ags7*log(1+exp((v(source,drain)-ags6)/ags7)) )} *Gate-drain capacitance C_GD gate drain {agd1} TC=0,0 gC_CGD1 gate drain Q={(0.5*ags2*ags4*log(1+exp((v(gate,drain)-ags3)/ags4))+ + agd2*agd4*log(1+exp((v(gate,drain)-agd3)/agd4))+ + agd5*agd7*log(1+exp((v(gate,drain)-agd6)/agd7))+ + agd8*agd10*log(1+exp((v(gate,drain)-agd9)/agd10)))} *Source-drain capacitance C_SD source drain {asd1} TC=0,0 gC_CSD1 source drain Q={(asd2*asd4*log(1+exp((v(source,drain)-asd3)/asd4))+ + asd5*asd7*log(1+exp((v(source,drain)-asd6)/asd7))+ + asd8*asd10*log(1+exp((v(source,drain)-asd9)/asd10))+ + asd11*asd13*log(1+exp((v(source,drain)-asd12)/asd13)) )} .ends