Design of a High Frequency, Low Loss eGaN
Converter with Reduced Parasitic Inductances

  

APEC
March 17 – 21, 2013

"Design of a High Frequency, Low Loss eGaN Converter with Reduced Parasitic Inductances"
Speaker: David Reusch, PhD; Director of Applications Engineering, Efficient Power Conversion Corporation
Location: Long Beach, CA
 

Abstract:
The demand for future power supplies to achieve higher output currents, smaller size, and higher efficiency cannot be achieved with conventional technologies. There are limitations in the current devices switching figure of merit, packaging parasitics, and design layouts that prevent operating with high frequency and low loss. The emergence of gallium nitride (GaN) transistors providing improved switching dynamics and low parasitic packaging offers the opportunity to improve high frequency performance. With GaN transistors, the high frequency switching loss is increased by the parasitic inductances generated in circuit layout. This paper will discuss the impact of design parasitics on circuit performance for eGaN®FETs and propose improved designs that can reduce parasitic inductances, providing improved high frequency performance.