Designers of point of load (POL) converters used in 24 VDC systems traditionally have had to decide between the high cost of an isolated converter and the low frequency and efficiency of a buck converter. When compared with the 12 V POL converter common in computing systems, the higher voltage of the 24 V POL converter increases FET voltage to at least 40 volts to accommodate switch-node ringing and increases commutation and C_OSS losses. eGaN FETs, from EPC, offer ultra-low Q_GD for low commutation losses and low Q_OSS for lower losses when charging and discharging the output capacitance. In addition, the innovative Land Grid Array (LGA), wafer level packaging of EPC’s eGaN FETs allow ultralow inductance in both the high frequency power loop and gate drive loop, and most importantly, the path common to these loops, known as the common source inductance (CSI) to help minimize current commutation losses. Low charge and CSI of eGaN FETs allow designers to push power density higher by pushing frequency higher without the efficiency penalty of traditional MOSFETs.

David Reusch, Ph.D., Director, Applications
Stephen L. Colino, V.P., Sales & Marketing

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