常見問題

eGaN® Devices in Circuits

In general it is not possible to put devices in series because they will not share the voltage during dynamic transients. EPC has a great selection of 200 V FETs that can be found here.

The substrate pin must always be connected to the source pin on the PCB regardless of the voltage potential of the source pin sits at.

Example:  half bridge high side FET.  The substrate pin would be connected to the switch node same as the source pin.

The best way to think about it is to forget it is a substrate pin and treat it like it is a source pin and connect accordingly.

The HS and LS input pins of the EPC2152 are referenced to ground and they do not have to be isolated from the logic ground.

The optimum dead time is obtained with an adaptive algorithm that reduces (or increases) the dead time so that the switching happens always at the point where the voltage has already changed.For more information on optimizing deadtime please view the webinar Understanding the Impact of Dead-time, QRR, and COSS

EPC works with many semiconductor partners that provide complementing drivers and controllers for EPC GaN solutions. A list of current solutions can be found on the eGaN Drivers and Controllers page. Also, please view the webinar Gate Drivers for GaN FETs

Yes, a push-pull through a 1:1 gate drive transformer with CT primary and secondary is possible:  Primary - Two EPC21601 driving a CT primary with the CT connected to 12V,  Secondary - Use the CT and one of the outside winding to create a 6V push pull gate drive.  It will double the drive current.  Maybe have a Zener diode clamp to protect the gate on the -6 negative swing. You can think of the EPC21601 as a low side gate driver + medium power GaN FET with an Open drain output.

Assuming you need high speed gate driving, one good choice is from TI. The LMG1210 is TI's 200 V GaN gate driver that can take up to 300 V transients. The LMG1210 works up to 50 MHz under some conditions, so it should be fine at 6.78 MHz.  It has programmable dead time, which is nice, or the dead time can be controlled externally. Another option to consider is the 650 V GaN gate driver, NCP51820, from ON Semi. The ecosystem of GaN friendly controllers and drivers can be found on the eGaN Drivers and Controllers page. Also, please view the webinar Gate Drivers for GaN FETs

More details on voltages, currents or power requirements are needed to optimize the performance. For instance, if the design is operating at 10% load, efficiency is typically low. One note on the coil design: it looks like you are attributing low efficiency to the amplifier but in WiPo systems the coil is an integral and critical component. Coil inductance, tuning schematic, coupling factor, rectifier, load range need to be comprehended. The board can operate in 50°C as long as none of the components exceed rated max. temperatures during operation; use an IR camera to verify operating temperatures.

The answer is yes I see a problem.  Specifically with VBoot.   However, Vdd and Vin can be tied together and use a common 12V supply. The rules: Vin = Main Input supply.  Connect to the drain of the high side switch.  Voltage is independent Vdd when Vdd = 12V.  We do not recommend you apply Vin before Vdd for any sustained period of time; both going up at the same time is fine. Vdd = 12V supply for driver itself.  All operating bias current is consumed from this pin.  It is recommended that Vdd powers up at the same time or before Vin.   Newer generations of EPC GaN solutions eliminates the potential issue between Vin and Vdd; VBoot is generated by the driver.  Do not attempt to supply your own power source.  There is active regulation of VBoot internally addressing specific operating conditions during switching to protect the high side gate drive voltage.

Yes all parts have spice and thermal models which can be found on the Device Models page.

The choice of measurement method depends on your thermal design.  If you have the top of the FET exposed, then yes, a thermal camera is a good idea.  Use non-reflective black paint on top of the FET.  Yes, you are correct, need to be careful of reflections. A paint to use:  Testors flat black enamel, 1149.  You can also use a paint pen, Testor 2549.  The pen is convenient, but the 1149 paint has been well characterized. You can also use Scotch Brand 88 black electrical tape, which has a reported emissivity of 0.95 to 0.96. An EPC apps engineer said of Testor 1149 paint: “I usually apply it with a toothpick, and it takes a bit to dry.” If you wish to use a thermal probe, then you can glue it to the side or top of the FET.  The junction (the section that generates the heat) is the bottom of the FET, the side that is very close to the board.  So, perhaps a probe on the lower part of the side would give a good result.  It sounds like you don’t have a heat sink on top, so there may not be a big thermal change between the junction and the top of the FET. 

If you download the Altium footprint library they include the step files. Download Altium footprint library

The operating frequency of our demo boards are based on our control system. Our devices work over 400kHz to ~2Mhz so there is no problem if you use your own controller to adjust the frequency. Working at higher frequency you will need to be very careful of layout since the effect of parasitic inductance will be more obvious at high frequency. The other thing you need to consider is even though GaN power devices have very small QG and QOSS, the switching loss will still be higher than low operating frequency. Working at higher frequency you can reduce ESR of buck inductance, so you can reduce loss.

Yes! The easiest way to select the GaN device to fit your voltage and current ratings is to use the Product Selector Guide for eGaN® FETs and ICs.

Yes, there is an example of a 3-phase inverter in the June 2021 edition of Bodo's Power Systems. The 3-phase inverter has basically the same concept as you see for each of the half bridges.

What is important when dealing with GaN FET is always using gate drivers which are made for GaN FET. A typical gate driver for a GaN FET has two outputs. One output is to switch on, the other to switch off - Details of this can be found in the webinar High-perforamnce layout techniques to maximize GaN device performance and referring to the "Demonstrations/drawings on Gate Loop Inductance slide".

On the GaN FET Selection Tool for Buck Converters page, enter your specifications where indicated and it will give you recommendations on which EPC parts will best meet your needs.

No. The gate driver must have two outputs. This is recommended from GaN FET and adjusted even if you want to add resistor 0 ohm. This was discussed in our webinar, Gate Drivers for GaN FETs.

Regarding EPC9146KITA, the EPC9147 controller board is programmed, but needs to be matched to a motor.  It needs the parameter table loaded.  All our demo boards have a quick start guide that describes the design and functionality of the board. There is a separate quick-start guide for EPC9147 controller board, on which page 7 shows a Quick Start procedure.  We worked with Microchip on the EPC9147 board  Their MotorBench development tools help. 

This will not work.  The 17A datasheet number is a test parameter to verify the minimum transconductance limit of the FET in production.   In other words, we do not guarantee the FET will support any drain currents higher than 17A regardless of the time duration.  The channel will saturate and begin to limit the current above 17A. You need to choose a FET with a pulse rating of 30Amp or greater just to support the current.  The SOA curve will limit the power.

You can drive three eGaN FET in parallel with only one driver, but each eGaN will need there own Rg, means if you use three eGaN in parallel that you will need three turn-on Rg (three turn-off Rg). You will need to be careful of layout, we hope that the layout loop and common source inductance should be same for each FET, since we want the current is average shared by three FETs.

  1. The VCharge caps, C10-C14 discharges through the Lidar every time Q1 is turned on.
  2. Before the next cycle, these capacitors have to be charged through the Capacitor recharge resistances R2 to R6, with a time constant determined by the parallel combination of R2 to R6.
  3. The fastest rate at which you can repeat the pulse is determined by this R1-R6 X C10 to C14 time constant. You will have to reduce the Cap Recharge resistance to improve the charge time and beef up the Capacitors to have a longer hold up time..
  4. Remember this board is designed for a lower repetition rate, resonant discharge of cap to zero voltage every time FET turns on. Hence modification of board will be necessary. Please review AN027 Getting the most out of eGaN FETs, it will give you a good insight.. after you review the design equations on this.

EPC’s eGaN® FETs and ICs will displace their silicon counterparts over the next few years due to superior performance and affordable costs. EPC has published several application notes and white papers on using these high-performance power devices which can be found on the Design Support page. EPC has also authored multiple textbooks that can be purchased at Amazon.com or through EPC’s web site.

Titles include:

GaN Transistors for Efficient Power Conversion
Wireless Power Handbook

We also have a series of video presentations showing how to use and applications for eGaN FETs.

Generally, the eGaN FET should be treated as any other MOSFET, keeping in mind that it does have the capability of higher performance operation because of its relatively low total gate charge (Qg) and small CRSS. Some general guidelines:

  • Drive the gate with 5 V, keep max gate voltage below 5.5 V. There are several ICs available to make this task easy.
  • Minimize gate source circuit impedance. It is advisable keep the gate source loop as small as possible, even at the cost of longer paths in drain circuit.
  • Use a low impedance driver
  • There are driver IC’s developed to optimize the performance of eGaN FETs in circuit. For a list of current available eGaN FET optimized IC’s please see the eGaN Drivers and Controllers page.

The “Using Enhancement Mode GaN-on-Silicon Power FETs application note, has further information. In addition, land pad layouts that minimize inductance can be found on all EPC data sheets on the Product Selector Guide for eGaN FETs and ICs page. Chapter 3 of the book titled, “GaN Transistors for Efficient Power Conversion” covers this topic in detail. Layout techniques to minimize switching time and voltage overshoot can be found in the white paper Impact of Parasitics on Performance and the white paper Optimizing PCB Layout. There is also a video that you can review at How to GaN 05: Design Basics – Layout.

eGaN devices have a very low temperature coefficient for their threshold voltage. This gives the user added safety margin despite the lower threshold voltages at room temperature. The Miller Capacitance, CGD of EPC eGaN devices is also very low, hence the switching speed is quite high; it can be turned off in a few nano seconds. In order to avoid dv/dt turn-on, it is critical to have very low impedance in the gate-source circuit as well as a low impedance pull down for the gate circuit. There are available gate drivers designed specifically for eGaN devices that will take care of many of these requirements. A list of GaN compatible drivers and controllers can be found on the eGaN Drivers and Controllers page. For more tips on driving eGaN FETs, see eGaN FET Drivers and Layout Considerations.

It should also be noted that eGaN devices have a very low temperature coefficient for their threshold voltage. This gives the user added safety margin despite the lower threshold voltages at room temperature. The ratios of CGD to CGS are quite good in holding the device off under a dV/dt condition. This is a capacitive divider, so care must be taken in the gate drive to have a low resistance turn off and good layout such that inductance is minimized in the turn off loop to keep the effective impedance low. The magnitude will depend on dV/dt and voltage. Gate drivers designed specifically for eGaN FETs are listed on the eGaN Drivers and Controllers page

eGaN Devices are positive temperature coefficient devices and are good candidates for parallel operation. However, since these devices can switch up to 10x faster than standard silicon FETs, special care must be taken in the layout and driving aspects of this configuration. EPC has written aan application note identifying the best paralleling configuration. Please refer to the Effectively Paralleling Gallium Nitride Transistors for High Current and High Frequency Applications application note.

The limiting factor for output power in most high-density converters is junction temperature, which prompts the need for more effective thermal design. The chip-scale packaging of eGaN also offers six-sided cooling, with effective heat extraction from the bottom, top, and sides of the die. A This high-performance thermal solution implemented to extend the output current capability of eGaN-based converters is presented in How2AppNote 012: How to Get More Power Out of a High-Density eGaN -Based Converter with a Heatsink.

EPC’s eGaN FETs and ICs are superb for wireless charging and wireless power applications! Wireless power is ready to be incorporated into our daily lives. Transmitters can be placed in furniture, walls, floors, to efficiently and economically power or charge our electronic and electrical devices. There are a couple of popular wireless power architectures available in the market. The capability of eGaN FETs and ICs to operate efficiently in the multi-MHz range offers a unique opportunity; enabling large surface area transmission, spatial freedom for placement of receiving devices, and the ability to power multiple devices simultaneously. We have many resources discussing how to apply eGaN power devices for wireless power. Please visit the Wireless Power page for more information.

EPC’s eGaN FETs and ICs are superb for applications in RF power amplifiers – especially in envelope tracking. Today Power Amplifiers (PA) commonly use depletion mode GaN FETs since they are capable of switching at several hundreds of MHz. The typical efficiency of PA is in the 20 to 30% since the Peak to Average Ratio (PAR) is very low. With the emerging technologies like LTE for wireless, the demand for power is going up and several new techniques like Envelope Tracking (ET) – where the voltage feeding the power amplifier is modulated corresponding the modulating signal – are evolving to improve the efficiency of PAs. eGaN FETs and ICs can switch at several tens of MHz at the voltage of interest in PAs, enabling the adoption of efficient Envelope Tracking architectures in these applications for improving the efficiencies. See the Envelope Tracking page more information on eGaN FETs and ICs in Envelope Tracking applications.

In Class D audio systems, the audio performance is impacted by the FET characteristics. GaN FETs enable higher fidelity Class D Audio Amplifiers.

The low on resistance and low capacitance of the eGaN FET enables high efficiency and lowers open loop impedance for low Transient Intermodulation Distortion (T-IMD). The fast switching capability and zero reverse recovery charge enable higher output linearity and low cross over distortion for lower Total Harmonic Distortion (THD).

For more information on eGaN FETs in Class-D audio amplifier applications and a list of available reference designs visit the Class D Audio Amplifiers page.

eGaN FETs have a distinct advantage over silicon MOSFETS in hard switching applications because of the reduction of two key parameters – QGD and QRR,both of which have little impact in resonant and soft-switching converters. It has been demonstrated that eGaN FETs can also provide significant improvements in resonant and soft-switching applications when compared to Si MOSFETs by offering reduced output charge, QOSS, and gate charge, QG.

For more information, please refer to the white paper eGaN FETs in High Frequency Resonant Converters.

Using eGaN FETs and ICs in these designs reduces switching losses resulting in higher efficiency and/or higher switching frequency. Inverter size and cost are dominated by thermal management and the passive elements used for bulk energy storage and filtering. Using eGaN FETs and ICs to increase efficiency and/or increase switching frequency can reduce the overall size and cost of the power inverter. For more information visit the Power Inverter Applications page.

The use of LEDs for illumination (not just backlighting) has proliferated in recent years and there are numerous applications and topologies. The EPC9001C and EPC9078 development boards can be used to create LED backlighting solutions with very high contrast ratio, but are designed for buck / half-bridge type topologies. For anyone experienced in the art it is possible to operate this ‘backwards’ as a synchronous boost – noting that the input PWM will now be complimentary to what is required. Care should be taken in doing so as the output bus voltage can easily be boosted above the rated maximum voltage.

To get more information about EPC’s growing list of development and demo boards, or to purchase these boards, please see the Demo Boards page.

The main question here would be the choice of topology to be employed. The EPC9001C and EPC9078 development boards can be used to create LED backlighting solutions with very high contrast ratio, but are designed for buck / half-bridge type topologies. For anyone experienced in the art it is possible to operate this ‘backwards’ as a synchronous boost – noting that the input PWM will now be complimentary to what is required. Care should be taken in doing so as the output bus voltage can easily be boosted above the rated maximum voltage.

To get more information about EPC’s growing list of development and demo boards, or to purchase these boards, please see the Demo Boards page.

EPC has worked with industry leaders to test high-reliability GaN products for military and space applications. These products have shown excellent radiation performance under Total Ionizing Dose (TID) and Single Event Effects (SEE) environments.  For more information visit the Radiation Tolerant Enhancement Mode Gallium Nitride FETs page.

It is important to keep the max gate voltage below 6V for long term reliability. To make this easy for the designer, we have developed drive level shifters, and discrete gate drivers that not only manage drive voltage, but also manage deadtime. For a detailed description of our recommended discrete solution please see the article How2 Get The Most Out Of GaN Power Transistors.

In June of 2011, Texas Instruments announced the industry’s first eGaN FET driver. Subsequently additional GaN compatible driver and controller options have become available in the market. A list of known partner IC’s is maintained on the eGaN Drivers and Controllers page.

To make this easy for the designer, in June of 2011, Texas Instruments announced the industry’s first eGaN FET driver. The LM5113 is a 100V half-bridge driver addressing a wide range of power converter topologies. Subsequently additional GaN compatible driver and controller options have become available in the market.

A list of known partner IC’s is maintained on the eGaN Drivers and Controllers page.

Additionally, we have developed drive level shifters, and discrete gate drivers that not only manage drive voltage, but also manage deadtime. For a detailed description of our recommended discrete solution please see the article “How2 Get the Most Out of GaN Power Transistors”. It should also be noted that eGaN devices have a very low temperature coefficient for their threshold voltage. This gives the user added safety margin despite the lower threshold voltages at room temperature.

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