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Practical Layout Techniques to Fully Extract the Benefits of eGaN FETs

分類: Articles
Practical Layout Techniques to Fully Extract the Benefits of eGaN FETs

The trend for electronics is to continually push towards miniaturization while increasing performance. With silicon MOSFET technology fast approaching its theoretical limit, enhancement mode gallium nitride (eGaN®) FETs from EPC have emerged to offer a step change improvement in power FET switching performance, enabling next generation power density possibilities by decreasing size and boosting efficiency. This article will explore the recommended layout techniques required to fully extract the benefits of EPC’s eGaN FETs.

By: Ivan Chan & David Reusch, Ph.D.
EEWeb –Modern Printed Circuits
August, 2015
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