Motivation

eGaN FETs are capable of switching much faster than Si MOSFETs, requiring more careful consideration of PCB layout design to minimize parasitic inductances. Parasitic inductances cause higher overshoot voltages and slower switching transitions. This application note reviews the key steps to design an optimal power stage layout with eGaN FETs, to avoid these unwanted effects and maximize the converter performance.

Impact of parasitic inductance on switching behavior

As shown in figure 1, three parasitic inductances can limit switching performance 1) power loop inductance (L_loop), 2) gate loop inductance (L_g), and 3) common-source inductance (L_s). The chip-scale package of eGaN FETs eliminates any significant inductance within the transistor itself, leaving the printed circuit board (PCB) as the main contributor. Each parasitic inductance is a consequence of the total area encompassed by the dynamic current path and its return loop. (See WP009: Impact of Parasitics on Performance).

Class-D audio amplifiers have traditionally been looked down upon by audiophiles, and in most cases, understandably so. Switching transistors for Class-D amplifiers have never had the right combination of performance parameters to produce an amplifier with sufficient open-loop linearity to satisfy the most critical listeners. This restricted the classical analog modulator Class-D systems to lower-power, lower-quality sound systems.

To accomplish the required headline marketing THD+N performance targets, Class-D amplifiers have had to resort to using large amounts of feedback to compensate for their poor open-loop performance. By definition, large amounts of feedback introduce transient intermodulation distortion (TIM), which introduces a ‘harshness’ that hides the warm subtleties and color of the music that were intended for the listening experience.