Reliability Report - Phase 16

This Phase 16 Reliability Report documents continued work using test-to-fail methodology and adds guidelines for improving thermo-mechanical reliability.

Compared to the Phase 15 Reliability Report, this version presents expanded data and analysis. It now includes a general overview of the wear-out mechanisms of primary concern for a given application, which is intended as an introduction to readers new to GaN reliability.

Siddhesh Gajare, Ph.D.,1 Duanhui Li, Ph.D.,1 Ricardo Garcia,1 Gerald Adriano,1 Angel Espinoza,1 Han Gao, Ph.D.,1 Gordon Stecklein, Ph.D.,1,2 Shengke Zhang, Ph.D.1

1 Efficient Power Conversion 2 SkyWater Technology

What is Covered in This Report:

  • SECTION 1: DETERMINING WEAR-OUT MECHANISMS USING TEST-TO-FAIL METHODOLOGY
    Section 1 describes the benefits of testing to failure and how this methodology leads to progress in GaN reliability by revealing a device’s intrinsic failure mechanisms.
  • SECTION 2: USING TEST-TO-FAIL RESULTS TO PREDICT DEVICE LIFETIME IN A SYSTEM
    Section 2, which is new to this version of the report, describes how to forecast the reliability of a system in a realistic mission profile that combines periods of substantial and minor stress.
  • SECTION 3: WEAR-OUT MECHANISMS
    The fundamental wear-out mechanisms are discussed individually in Section 3. Compared to previous versions of this report, the thermo-mechanical wear-out mechanisms and overvoltage guidelines include significant new material.
    • 3.1 Gate Wear-Out
    • 3.2 Drain Wear-Out
    • 3.3. Current Density Wear-Out
    • 3.4 Thermo-Mechanical Wear-Out
    • 3.5. Mechanical Stress Wear-Out
  • SECTION 4: MISSION-SPECIFIC RELIABILITY PREDICTIONS
    Section 4 reports on the reliability of GaN in specific applications.
    • 4.1. Solar Application Specific Reliability
    • 4.2 DC-DC Application Specific Reliability
    • 4.3 Lidar Application Specific Reliability
  • SECTION 5: SUMMARY AND CONCLUSIONS
  • APPENDIX: Solder Stencil Design Rule for Reliable Assembly of PQFN Packaged Devices
    A method for optimizing solder stencils for reliable assembly is provided in the Appendix which shows how to determine the solder stand-off height of Power Quad Flat No-Lead (PQFN) packaged GaN FETs.