常見問題

Assembling eGaN® FETs and ICs

eGan devices can be assembled easily like any other Land Grid Array (LGA) device. Users can generally apply standard surface mount techniques to successfully attach EPC’s eGaN FETs onto standard PCBs. EPC has published an application note as well as quick-start guides for die attach and die removal. These can be found on the Assembly Resources page.

All EPC eGaN devices are MSL-1 rated.

EPC uses SAC405 (95.5/4.0/0.5 Sn/Ag/Cu) or 97.5/2.5 Sn/Ag for our PbF solder bumps.

The under bump metal layers can be Ti / Cu with SAC405 solder bumps or Ti / Cu / Ni with SN97 solder bumps.

Yes, a via can be placed directly under a bump, but care must be taken to ensure that the via is tented (covered with solder mask) in order to prevent solder from wicking into the hole during the reflow process, and to prevent voltage clearance issues due to exposed copper in proximity to the die. A non-filled via can cause the die to tilt or not connect the bump to the pad properly. The recommended via design is a micro-via with a 6mil hole diameter and an annular ring diameter not to exceed the width of the pad and MUST be filled with either a non-conductive or conductive filler. For general tips on device layout on a PCB, go to Optimizing PCB Layout.

EPC currently uses Kester NXG1 Type 3 SAC305 and Kester NP505-HR SAC305 Type 4 solder pastes for soldering eGaN devices. Both pastes are no-clean flux with 88.5% metal.

The figure below shows the recommended reflow profiles for eGaN devices based on the solder paste manufacturers’ recommendations for the pastes. The vendor recommended reflow profiles should always be followed for the paste being used.

A laser-cut stainless steel stencil of 100-µm thickness is recommended. A smooth wall laser-cut stencil is more likely to release the desired dispense volume. Type 3 solder paste requires a larger opening than Type 4 solder, and recommendations are available for both in Assembling eGaN FETs and Integrated Circuits application note. In the case that a stamped stencil must be used, it may be necessary to enlarge the opening slightly to compensate for proper solder release volume.

EPC’s eGaN FETs and ICs can be mounted directly onto PC boards without added solder by using a tacky flux to hold the part in place while reflowing the solder. An example of an acceptable PbF process uses Kester TSF6502 no-rinse flux. Quick reference die attach and removal instructions, as well as videos, are available on the Assembly Resources page.

EPC recommends the use of no clean flux solders. However, to prevent the formation of thermal and electrical dendrites, it is recommended to clean the flux from the board even if no-clean flux is used. EPC uses Kyzen Aquanox® A4625 chemical in a Nu/Clean AquaBatch XL standard system manufactured by Technical Devices Company to remove the no clean flux.

If a no-clean flux is used and it is not rinsed off, a post-reflow bake for a minimum of 60 minutes at 150°C is recommended. This ensures that the no clean flux is properly cured and helps prevents dendrite formation.

If a water rinseable flux is used, the eGaN device needs to be rinsed on all four sides to ensure proper flux removal. A tilted device can obstruct the flow of the rinse and cause flux to remain trapped under the die. For this reason, using a no rinse solder flux with low ionic content and then rinsing the no rinse flux is recommended. For more information, please see our assembly application note: Assembling eGaN FETs and Integrated Circuits.

At this time, EPC does not recommend using a water rinseable solder flux for the PbF devices. If a water rinseable flux is used, the eGaN device needs to be rinsed on all four sides to ensure proper flux removal. A tilted device can obstruct the flow of the rinse and cause flux to remain trapped under the die. For this reason, using a no rinse solder flux with low ionic content and then rinsing the no rinse flux is recommended. For more information, please see our assembly application note: Assembling eGaN FETs and Integrated Circuits.

Underfill should be used in applications where the board is exposed to moisture. Moisture and other contaminants may provide an environment that allows dendrite growth. For 150ºC-capable EPC devices, some available underfills are Hysol FP4531 and AI Technology MC7685-UFS.

Please note that the below response applies to the following LGA package devices: EPC2001C, EPC2007C, EPC2010C, EPC2012C, EPC2014C, EPC2015C, EPC2016C, EPC2019, EPC8002, EPC8004, EPC8009 and EPC8010.

EPC has determined that the die in the list above can withstand up to 200 psi without adverse effect to the die parametric performance. It is important to note that this number assumes there is not a severe assembly issue (i.e. die tilt) that could affect the attachment of the heat sink material and/or the uniformity of applied pressure.

There are many issues that can arise if proper PCB design rules not followed. These issues can be exacerbated by poor assembly techniques. There is a section in the application note Assembling eGaN FETs and Integrated Circuits that presents the many issues we have encountered and explains their origins. This section starts with item 15 on page 5 of the application note.