EPC GaN FETs are lateral devices built on a GaN Epitaxial layer with an isolation layer between the active device regions and the supporting Si substrate.
Small signal FET devices with different maximum voltage withstand capabilities from 5 V to 100 V FETs can be built on the same chip with passive devices such as resistor and capacitors. That forms the basic platform for constructing useful circuits integrated with GaN output devices.
The output devices can be configured as a half bridge or other topologies. And most importantly, the GaN output devices in IC platform vs. the discrete GaN FETs, are not compromised in performance figure of merit.
Traditional Si MOSFET structure is vertical conduction, called VDMOS, that are not easily integrated with small signal CMOS or bipolar devices.
The BCDMOS IC platform typically requires very high mask counts to integrate all the devices, and the output VDMOS devices are less efficient than the optimized discrete counterparts.
Lower voltage monolithic BCD platform (less than 40 V) uses LDMOS for easier integration with acceptable performance. However, both BCDMOS platforms suffer from substrate current conduction which could cause latch-up. Special layout techniques or use of expensive SOI structures are needed for isolating the output FETs, especially during diode conduction. Since there is no parasitic diode associated with GaN FETs, there is less concern about parasitic substrate current conduction.