A Better Power Package
GaN transistors are much smaller than their silicon counterparts. This size advantage translates into additional cost benefits to the producers, translating into additional cost benefits to the user. PCB real estate is very expensive. Smaller devices mean less real estate. In some cases, the smaller footprint and greater performance of GaN enables a new end product not possible with larger silicon parts.
For high voltage lateral GaN transistors, all of the electrical connections are located on the same side of the die, allowing for the elimination of complex, performance limiting two sided packaging common in vertical Si power MOSFETs. Chip-scale packaging is a more efficient form of packaging that reduces the resistance, inductance, size, thermal impedance, and cost of power transistors, enabling unmatched in-circuit performance.
EPC Chip-Scale Packaged FETs and ICs