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EPC publishes the schematic for all evaluation boards to allow for easy copy and paste of designs containing all critical components and a layout that supports optimal switching performance. Select the evaluation board of interest from our growing list of designs and find the schematic along with bill of materials and gerber files to get your design started.
EPC uses the standard MOSFET symbol for GaN FETs to make it easier for designers. Enhancement‐mode GaN transistors do not have a p–n body diode as in a silicon power MOSFET, but they do conduct in the reverse direction in a way that is like the diode in a power MOSFET. However, because there are no minority carriers involved in conduction in an enhancement-mode GaN transistor, there is no reverse recovery charge. QRR is zero, which is a significant additional advantage compared with power MOSFETs.
The GaN First Time RightTM PCB Layout Rules Webinar covers essential guidelines to ensure your GaN-based designs succeed from the start. In this webinar we will show how parasitic inductances impacts converter performance, recommend best practices to design the best PCB for EPC GaN FETs. Both DC/DC converters and motor drives applications will be analyzed. Learn how to avoid common pitfalls and achieve optimal performance in your GaN-based converter and motor drive designs. Whether you're new to GaN or looking to refine your layout techniques, this webinar is packed with insights to help you get it right the first time.
GaN transistors generally behave like power MOSFETs, but at much higher switching speeds and power densities, therefore layout considerations are very important and care must be taken to minimize the main layout parasitic inductances for the power loops and gate loops:
The recommended design for Optimizing PCB Layout with eGaN FETs (WP010) utilizes the first inner layer as a power loop return path. This return path is located directly beneath the top layer’s power loop allowing for the smallest physical loop size. Variations of this concept can be implemented by placing the bus capacitors either next to the high-side device, next to the low-side device, or between the low and high-side devices, but in all cases, the loop is closed in the inner layer right beneath the devices. A similar concept is also used for the gate loop, with the return gate loop located directly under the ON and OFF gate resistors.
Furthermore, to minimize the common source inductance between power and gate loops, the power and gate loops are laid out perpendicular to each other, and a via next to the source pad closest to the gate pad is used as Kelvin connection for the gate driver return path.
The switching waveforms for the eGaN® FET conventional and optimal layouts and Si MOSFET benchmark are shown in figure 10. Both eGaN® FET designs offer significant switching speed gains when compared to the Si MOSFET benchmark. For the eGaN® FET with the conventional layout, the high switching speed combined with loop inductance induces a large voltage spike. The optimal layout eGaN® FET offers a 40% reduction in voltage overshoot when compared to the 40 V Si MOSFET benchmark, while switching 5 times faster.
For higher-power applications, it may be necessary to place multiple transistors in parallel and have them behave as a single device. GaN devices parallel extremely well because:
However, to ensure good current sharing in dynamic conditions, it is also important to pay attention to the layout:
An example of a parallel layout with 4 devices in parallel is the EPC90135: 100 V, 45 A Parallel Evaluation Board
Many EPC parts are offered in a Wafer Level Chip Scale Package (WLCSP) using a fine pitch down to 400 µm. This means a proper PCB footprint design is essential for consistent and reliable assembly of the GaN device. Detailed recommendations can be found here How2AppNote008 - Designing PCB Footprint eGaN FETs ICs, and recommended land patterns (solder mask opening) and stencil designs are provided in each datasheet. EPC also provides an Altium Library with all the EPC footprints. The video Footprint Design – PCB CAD System Independent guides customers through a CAD-independent detailed explanation of how to create their own footprints.
EPC recommends the use of a Solder Mask Defined (SMD) pad over a Non-Solder Mask Defined (NSMD) pad for two reasons:
EPC recommended silkscreen design should include:
If you would like the EPC team to review your design once the schematic and layout are done, please submit request to [email protected]
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