In some situations, a designer might want to use a generic gate driver or controller. This is often possible (as an example in EPC9141 – 48 V – 12 V, 10 A Buck Converter) but there are a few points that need to be investigated, including:
- High-side bootstrap voltage “clamp” - for low-side FET reverse current conduction (reverse conduction voltage is as high as 2.5 V which can charge the bootstrap capacitor to over 7 V) for bootstrap power supply-driven half-bridge drivers.
- Under voltage lockout (UVLO) should be checked and is recommended to be in the range 3.6 V for disable and 4.0 V for enable.
- Since GaN devices can switch very fast, the gate driver should be able to withstand these high dv/dt; a capability > 100 V/ns is recommended.
- Minimum deadtime should be low enough to minimize deadtime losses, ideally in the 20-40ns range: Dead-Time Optimization for Maximum Efficiency
- A small, low-cost Schottky diode in parallel with the lower FET may be needed. See board EPC9141 – 48 V – 12 V, 10 A Buck Converter for an example.
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