GaN Design Support Center for EPC Products

Gallium nitride (GaN) is called a wide bandgap (WBG) semiconductor due to the relatively large bonding energy of the atomic components in its crystal structure. EPC’s enhancement mode Gallium Nitride transistors are based on the GaN HEMT (High Electron Mobility Transistors) device structure. This video HTG01 Material Comparisons provides an overview of these devices.

GaN FETs operate in a very similar manner to Si MOSFETs, and their main characteristics are explained in our white paper eGaN FET Electrical Characteristics. The main characteristics are explained in this video, HTG03 Performance Characteristics. We particularly described the reverse conduction mechanism for GaN FETs, which, although physically different from a Si MOSFET, results in very similar behavior as the body diode, just without reverse recovery.

Since EPC GaN transistors generally behave like n-channel power MOSFETs, common curve tracers, parametric analyzers, and automatic discrete device parametric testers that are used for an n-channel power MOSFET will be applicable for the characterization of GaN transistors as long as the guidelines in the EPC GaN Transistor Parametric Characterization Guide are followed.

Additional Resources

• Using eGaN FETs (AN003)
• eGaN FET Electrical Characteristics (WP007)
• Comparing Figure of Merit
• Characteristics of Second Generation eGaN FETs (AN013)
• eGaN FETs for Multi-Megahertz applications (AN015)
• eGaN^® FET Safe Operating Area (AN014)

Electrical modeling can be used to select the correct device for each set of application conditions. EPC has developed GaN Power Bench for this purpose:

Steps 2 and 3 can be performed iteratively to arrive at an optimized solution. An analytical approach to this process is also provided in our white paper Selecting eGaN FET Optimal On-Resistance.

Electrical Simulation

For more detailed electrical simulations, EPC utilizes a hybrid of physics-based and phenomenological functions to achieve a compact spice model with acceptable simulation and convergence characteristics, including temperature effects for conductivity and threshold parameters. These can be found on the EPC Device Models page, while the Circuit Simulation Using EPC Device Models provides an in-depth look at these models. Supported model formats include spice, P-Spice, Simplis/SIMetrix, Spectre, and T-Spice.

Thermal Simulation

An overview of thermal modeling is provided in the application note Thermal Performance of EPC eGaN FETs.

It is important to note that EPC GaN FETs can take advantage of dual-sided cooling to maximize their heat dissipation capabilities in high-power density designs. This is covered in detail in How2AppNote012 - How to Get More Power Out of an eGaN Converter. The thermal design can be further optimized by using the GaN FET Thermal Calculator.

Additional Resources

• How2AppNote012 - How to Get More Power Out of an eGaN Converter
• Thermal Management of Chip-Scale Devices
• Improving Thermal Performance of Chip-Scale Packaged Gallium Nitride Transistors
• Webinar: Thermal Management of GaN FETs

Just like Si MOSFET, to maximize the performance of GaN FETs, an appropriate gate driver needs to be selected, which is covered in our webinar Gate Drivers for GaN FETs. In general EPC’s eGaN FETs’ gates work like 5V logic: 5V is ON, and 0V is OFF. Many optimized GaN gate drivers and controllers are available, for best performance and gate protection (Gallium Nitride (GaN) FET Drivers and Controllers).

In some situations, a designer might want to use a generic gate driver or controller. This is often possible (as an example in EPC9141 – 48 V – 12 V, 10 A Buck Converter) but there are a few points that need to be investigated, including:

1. High-side bootstrap voltage “clamp” - for low-side FET reverse current conduction (reverse conduction voltage is as high as 2.5 V which can charge the bootstrap capacitor to over 7 V) for bootstrap power supply-driven half-bridge drivers
2. Under voltage lockout (UVLO) should be checked and is recommended to be in the range 3.6 V for disable and 4.0 V for enable.
3. Since GaN devices can switch very fast, the gate driver should be able to withstand these high dv/dt; a capability > 100 V/ns is recommended
4. Minimum deadtime should be low enough to minimize deadtime losses, ideally in the 20-40ns range: Dead-Time Optimization for Maximum Efficiency
5. A small, low-cost Schottky diode in parallel with the lower FET may be needed. See board EPC9141 – 48 V – 12 V, 10 A Buck Converter for an example

EPC maintains a list of compatible Gallium Nitride (GaN) Drivers and Controllers, as well as offers a family of integrated products that combine GaN FETs and driver ICs for the highest switching performance and highest power densities.

EPC also offers a family of integrated products that combine GaN FETs and driver ICs for the highest switching performance and highest power densities:GaN Integrated Circuits (epc-co.com)

GaN transistors generally behave like power MOSFETs, but at much higher switching speeds and power densities, therefore layout considerations are very important and care must be taken to minimize layout parasitic inductances.

The recommended design for Optimizing PCB Layout with eGaN FETs (WP010) utilizes the first inner layer as a power loop return path. This return path is located directly beneath the top layer’s power loop allowing for the smallest physical loop size. Variations of this concept can be implemented by placing the bus capacitors either next to the high-side device, next to the low-side device, or between the low and high-side devices, but in all cases, the loop is closed in the inner layer right beneath the devices. A similar concept is also used for the gate loop, with the return gate loop located directly under the ON and OFF gate resistors.

Furthermore, to minimize the common source inductance between power and gate loops, the power and gate loops are laid out perpendicular to each other, and a via next to the source pad closest to the gate pad is used as Kelvin connection for the gate driver return path.

Additional Resources

• How to Design an eGaN FET-Based Power Stage with an Optimal Layout (How2AppNote007)
• Best Practices for Integrating eGaN FETs
• Impact of Parasitics on Performance (WP009)

Paralleling Recommendations

For higher-power applications, it may be necessary to place multiple transistors in parallel and have them behave as a single device. GaN devices parallel extremely well because:

• The R_DS(ON) has a positive temperature coefficient, so in the ON-state the current will self-balance based on each device temperature
• The Q_G of GaN FET is much lower than comparable Si MOSFET, therefore the requirements and the losses in the gate driver are minimized
• The V_TH of GaN FET is very stable over temperature, as compared to a strongly negative temperature coefficient for Si MOSFET, this allows good current sharing also during switching events

However, to ensure good current sharing in dynamic conditions, it is also important to pay attention to the layout:

• All parasitic inductances in the layout should be kept as similar as possible for each paralleled device, both for the power loop and gate loop
• For high-performance applications, we recommend a layout technique of paralleling half-bridges instead of single devices: Paralleling High Speed GaN Transistors (AN020).

An example of a parallel layout with 4 devices in parallel is the EPC90135: 100 V, 45 A Parallel Evaluation Board

Footprint Recommendations

Many EPC parts are offered in a Wafer Level Chip Scale Package (WLCSP) using a fine pitch down to 400 µm. This means a proper PCB footprint design is essential for consistent and reliable assembly of the GaN device. Detailed recommendations can be found here How2AppNote008 - Designing PCB Footprint eGaN FETs ICs, and recommended land patterns (solder mask opening) and stencil designs are provided in each datasheet. EPC also provides an Altium library file with all EPC footprints here: EPC Device Models. The video Footprint Design – PCB CAD System Independent guides customers through a CAD-independent detailed explanation of how to create their own footprints.

EPC recommends the use of a Solder Mask Defined (SMD) pad over a Non-Solder Mask Defined (NSMD) pad for two reasons:

• A Solder Mask Defined (SMD) footprint yields lower inductance and improves alignment during reflow.
• A Non-Solder Mask Defined (NSMD) footprint has a higher probability of die misalignment during reflow, which can reduce the effective copper contact area thereby degrading the solder joint and current carrying capability of the device.

EPC recommended silkscreen design should include:

• 4 corner registration marks outlining the part shape.
• Lines drawn with an open narrow dash: a solid line rectangle surrounding the part, thus preventing flux from flowing away from the die during the reflow process, can create a flux dam and trap flux under the part.
• Unique Pin one identifier.

To ensure high reliability and to extract maximum performance from eGaN devices, it is important to follow some simple PCB design and assembly guidelines, which are presented in Assembling eGaN FETs and Integrated Circuits.

When starting a new production process, it is common to set up incoming visual inspections. To simplify this process, detailed descriptions of the EPC FETs and ICs physical characteristics including the visual criteria all devices must meet before they are released for shipment to customers are given in the Enhancement Mode GaN FETs and ICs Visual Characterization Guide

For additional information on assembly guidelines, visit our page Assembly Resources.

For dynamic measurements, the increase in switching speed offered by GaN transistors requires good measurement technology, as well as good techniques to capture important details of high-speed waveforms. AN023 Accurately Measuring High-Speed GaN Transistors application note focuses on how to leverage the measurement equipment for the user’s requirement and measurement techniques to accurately evaluate high-performance GaN transistors. In particular, differential probes specifically intended for this type of measurement are recommended like Tektronix IsoVu, LeCroy DL-ISO, and PMK Firefly probes.