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With the advent of next-generation GaN transistors operating in the 40 V to 15 V range, RDS(on) specifications have reached the re¬markable level of hundreds of micro-ohms , significantly outperforming comparably-sized power MOSFETs. To fully capitalize on the advantages of these ultra-low resistance FETs, careful PCB layout is essential to prevent any additional re¬sistance that could undermine their performance. This article will examine various layout strategies for GaN FETs, analyzing how dif¬ferent PCB configurations affect added resistance for each design.
Bodo’s Power Systems
October 2025
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