How to Design an eGaN FET-Based Power Stage with an Optimal Layout
Oct 24, 2018
eGaN® FETs are capable of switching much faster than Si MOSFETs, requiring more careful consideration of PCB layout design to minimize parasitic inductances. Parasitic inductances cause higher overshoot voltages and slower switching transitions. This application note reviews the key steps to design an optimal power stage layout with eGaN FETs, to avoid these unwanted effects and maximize the converter performance.
Impact of parasitic inductance on switching behavior
As shown in figure 1, three parasitic inductances can limit switching performance 1) power loop inductance (Lloop), 2) gate loop inductance (Lg), and 3) common-source inductance (Ls). The chip-scale package of eGaN FETs eliminates any significant inductance within the transistor itself, leaving the printed circuit board (PCB) as the main contributor. Each parasitic inductance is a consequence of the total area encompassed by the dynamic current path and its return loop. (See WP009: Impact of Parasitics on Performance).
Figure 1: Equivalent circuit of an eGaN FET-based power stage with parasitic inductances and dynamic current loops highlighted
Optimal layout for an eGaN FET-based power stage
The smallest power loop and gate loop inductance can be achieved by taking advantage of an inner PCB layer to form an optimized return path. The decoupling capacitors are placed close to the drain of the high-side transistor. PCB vias are used to connect the ground terminal of the capacitors to the low-side source by way of the first inner layer, where the dielectric thickness is intentionally kept thin to keep the inductance low. An example of this optimal layout technique is shown in figure 2.
Figure 2: Optimal layout for an eGaN FET-based power stage, highlighting the dynamic current loop paths
The gate driver must be located very close to the gate and source terminals of each transistor or transistors it drives, and the bypass/ bootstrap capacitors and gate resistors should be positioned so that the gate current direction is orthogonal to the power loop. It is critical to separate the gate return current path from the power loop at the source terminal to minimize the common-source inductance. (See WP010: Optimizing PCB Layout and WP008: eGaN FET Drivers and Layout Considerations respectively).
How an optimal layout benefits converter performance
Converter systems with eGaN FETs inherently outperform comparable Si-based designs, and optimal layout techniques further enhance these benefits. Figure 3 demonstrates the eGaN advantage in a 48 V to 12 V buck converter operating at 500 kHz, comparing the EPC2045 100 V eGaN FET against a 100 V Si MOSFET in an S3O8 package. Both converters employ the optimal layout technique, but the tiny chipscale EPC2045 allows for considerably lower loop inductance than the larger Si MOSFET. Figure 3(a) shows that the eGaN version achieves 5x the voltage slew rate while maintaining the same peak overshoot voltage as the Si version, owing to the lower loop inductance combined with the fast switching capability of GaN. The faster switching edge has a tremendous impact on the system system performance, as indicated by the >2% higher peak efficiency in figure 3(b).
Figure 3: Comparison of a 48-to-12 V buck converter with EPC2045 eGaN FETs in the optimal layout, against a 100 V Si MOSFET example (a) switch node waveforms, (b) system efficiency.
Monolithic eGaN half bridge IC
Monolithic integration with an eGaN half bridge IC offers further improvement in loop inductance. For example, integrating a 12-to-1 V POL converter reduces the power loop inductance by 40% compared with a discrete solution. Figure 4 shows the EPC9204 POL power module using the EPC2111 monolithic half bridge eGaN IC, highlighting the ultra-dense power loop and gate loops achievable through integration. Further information can be found in AN018: GaN Integration for Higher DC-DC Efficiency and Power Density.
Figure 4: EPC9204 20 V, 10 A power module using EPC2111 monolithic eGaN half bridge IC, with power loop and gate loops highlighted.
With the faster switching speed of eGaN FETs, improved packaging and layout techniques are required to minimize parasitic inductance and fully utilize these advanced devices. Chipscale eGaN FETs reduce the packaging inductance to nearly zero, while enabling ultra-low inductance PCB power loops. Optimizing the PCB layout is a crucial step in achieving the maximum performance capability of eGaN FET-based designs.