Using eGaN™ FETs is very similar to using power MOSFETs. However, due to the significantly better performance, there are some design and test considerations to maximize performance.
eGaN FETs and integrated circuits from EPC have taken a very different approach to packaging power semiconductors – we have ditched the package altogether. EPC’s innovative wafer level, chip-scale packaging has enabled a new state-of-the-art in power density.
The increase in switching speed offered by GaN transistors requires good measurement technology, as well as good techniques to capture important details of high-speed waveforms. This application note focuses on how to leverage the measurement equipment for the user’s requirement and measurement techniques to accurately evaluate high performance GaN transistors.
In this application note, we will discuss paralleling high speed GaN transistors in applications requiring higher output current. This work will discuss the impact of in-circuit parasitics on performance and propose printed circuit board (PCB) layout methods to improve parallel performance of high speed GaN transistors.
Gallium nitride based transistors and ICs offer designers of power converters a path towards achieving higher output power, higher efficiency, and higher power density. This application note will address an eGaN FET module designed as a way for power-conversion systems designers to easily evaluate the exceptional performance of gallium nitride transistors.
While the thermal performance of traditional silicon MOSFETs is well understood, measuring the thermal performance of eGaN FETs requires some further explanation. This Applications Note investigates the testing method and results of thermal resistance measurements on eGaN FETs.
A basic limitation of a power transistor is temperature. Calculations of device temperature during operation assume that power dissipation is spread evenly over the entire active area of the device, which is not always true. This paper will describe the thermally derived Safe Operating Area (SOA) of power GaN FETs which demonstrate very good SOA characteristics while maintaining superior RDS(on). The paper will then compare thermally derived calculations with measured results.
An accurate circuit and device model is a valuable tool for developing new topologies, building successful designs, and shortening time to market. This article describes the status and use of EPC device models, and illustrates some important considerations when incorporating EPC eGaN devices into a circuit model.
The EPC GaN transistors generally behave like n-channel power MOSFETs. Common curve tracers, parametric analyzers, and automatic discrete device parametric testers that are used for an n-channel power MOSFET will be applicable for the characterization of GaN transistors. This applications note provides guidelines to characterize DC parameters using Tektronix 576 curve tracer, Keithley 238 parametric analyzer, TESEC 881-TT/A discrete device test system.
A detailed description of the EPC enhancement mode transistors and integrated circuits physical characteristics is given including the visual criteria all devices must meet before they are released for shipment to customers.
In this white paper we continue our exploration of optimization issues and look at the impact of dead-time on system efficiency for eGaN FETs and MOSFETs.
In this white paper the die size optimization process for selecting the eGaN FET optimal on-resistance is discussed and an example application is used to show specific results. Since ‘optimum’ means different things to different people, this process is aimed at maximizing switching device efficiency at a given load condition.
This white paper will explore the optimization of PCB layout for an eGaN FET based point of load (POL) buck converter, comparing the conventional designs and proposing a new optimal layout to further reduce parasitics.
With improvements in switching figure of merit provided by eGaN FETs, the packaging and PCB layout parasitics are critical to high performance. This white paper will study the effect of parasitic inductance on performance for eGaN FET and MOSFET based point of load (POL) buck converters operating at a switching frequency of 1 MHz, an input voltage of 12 V, an output voltage of 1.2 V, and an output current up to 20 A.
eGaN FETs differ from their silicon counterparts because of their significantly faster switching speeds and consequently have different requirements for gate drive, layout, and thermal management which can all be interactive.
In this paper the basic electrical characteristics of eGaN FETs are explained and compared against silicon MOSFETs. A good understanding of the similarities and differences between these two technologies is a necessary foundation for understanding how much we can improve existing power conversion systems.